> I have been successfully using the USRP to digitize NTSC video. However I > need to change > the system operation freq to 27 MHz. I am thinking of using cyclone's PLL > for generating the > 27 MHz clock for internal operation. But the problem is really feeding the > 27 MHz clock > to the ADC. I am going to use an unused FPGA output and use it to drive the > CLK_CODEC_A and CLK_CODEC_B signals.
That would work. > I am referring to the schematic for the FPGA (fpga.pdf). I will disconnect > R1012 and R1023, > and simply connect the output clock of the FPGA to the R1014 and R1015. I think you meant R1012 and R1013. That would work. Matt _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
