The GitHub Actions job "CI" on tvm.git/main has succeeded. Run started by GitHub user spectrometerHBH (triggered by spectrometerHBH).
Head commit for run: f20fa692d5dd71d875a9e310eae3e754169888fb / Bohan Hou <[email protected]> [TIRx][CUDA] Add PTX address expressions with immediate byte offsets (#20153) This PR adds `T.ptx.addr(base, byte_offset)` to the TIRx PTX dialect: a pure expression that folds a compile-time signed byte displacement into the PTX address operand, rendering as `[%N+imm]` instead of requiring a separate address computation before the instruction. - `tirx.ptx.addr` is an expression only in the outer PTX call's IR: the helper still receives the coerced base register, while the displacement becomes renderer metadata baked into the instruction text and the helper name (`_addr<slot>_p<imm>` / `_m<imm>`). - Table-level `allow_imm_offset` classification of address slots, with validation that rejects immediate offsets on operand classes that cannot take them (e.g. `tmem` addresses). - Immediate operands are now validated to be compile-time `IntImm` at CUDA codegen, with an actionable error pointing at explicitly-unrolled loops. - Displacements are range-checked to int32; zero offsets normalize to the bare form so existing helper names are untouched. Also includes a small test fix: `test_tirx_kernels_registry_correctness.py` accepts both the old and new MegaMoE kernel registry names (`deepgemm_fp8_fp4_mega_moe` / `sm100_fp8_fp4_mega_moe`), so the test works against tirx-kernels checkouts from either side of the rename. Tested with `tests/python/tirx/codegen/test_ptx_addr.py` (new, 12 cases), plus the full `tests/python/tirx/` suite on sm100. Report URL: https://github.com/apache/tvm/actions/runs/32161005007 With regards, GitHub Actions via GitBox --------------------------------------------------------------------- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
