ZephyrLi-pro opened a new pull request, #19776: URL: https://github.com/apache/tvm/pull/19776
This PR improves TIRx vectorization for RISC-V RVV targets. Fixed-width `T.vectorized` loops can be lowered to fixed LLVM vectors such as `<16 x float>`, which LLVM/RVV may scalarize into repeated scalar `flw/fsub.s/fsw` instructions. This PR rewrites fixed-width vectorized loops on RVV targets into scalable `T.vscale() * 4` chunks with lane masks, allowing LLVM to generate RVV load/store instructions instead. The change is limited to RISC-V RVV and does not enable the same automatic rewrite for Arm SVE. Tested on a RISC-V K3 board: Before: flw/fsub.s/fsw = 16/16/16, vle32/vse32 = 0/0 After: flw/fsub.s/fsw = 0/0/0, vle32/vse32 = 1/1 Also added a RISC-V LLVM codegen regression test. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected] --------------------------------------------------------------------- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
