tlopex opened a new pull request, #19729:
URL: https://github.com/apache/tvm/pull/19729
Fix the s_tir MetaSchedule sketch tests that no longer matched the design
spaces generated by current TVM:
* test_meta_schedule_schedule_rule_add_rfactor.py::test_cpu_argmax The
argmax workload and its expected sketches used the legacy `v: T.int32 = ...`
annotated-assignment syntax. The TIRx parser now lowers that form to a mutable
local-scalar buffer plus a store, which the rfactor/cross-thread-reduction
reducer matching correctly rejects (reduction combiner temporaries must be
immutable binds). Switch the temporaries to `v: T.let[T.int32] = ...`,
producing Bind nodes - the same canonical form te.create_prim_func emits for
comm_reducer based reductions - so AddRFactor generates the three expected
sketches again.
* test_meta_schedule_space_cuda.py (cap, dil, gmm, t2d, nrm, sfm, cbr, tbg)
and test_meta_schedule_space_cuda_async.py (c2d) Commit b46564618a (#18927)
expanded DefaultCUDA unroll_max_steps from {0, 16, 64, 512, 1024} to {0, 16,
32, 64, 128, 256, 512, 1024} without updating the expected SampleCategorical
decisions, so the recorded indices selected different unroll values than the
expected modules encode. Remap the decision indices (2->3, 3->6, 4->7) so each
test keeps sampling the same unroll value. The expected modules and all other
decisions are unchanged; every sketch was re-verified by replaying the trace
and structurally comparing against the expected module.
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