Hi all,
Recently, I'm helping my mentor research open source DL accelerators, and our short-term goal is to implement these accelerators on our own FPGA platform. Vta attracted me so much for its complete software tool chain and customizable architecture. I'm very glade to join you, it's realy a special attempt for me. I have successful run resnet-18 in my PYNQ-v2 by following [VTA Installation Guide](https://tvm.apache.org/docs/vta/install.html) and vta tutorials. Now I'm working on generate an optimal bitstream for other FPGA with more resources. Some problems are bothering me: 1.Where can I find the configuration information:"**HW_FREQ**" and "**HW_CLK_TARGET**" that mentioned in "VTA Intallation Guide---HLS-based Custom VTA Bitstream Compilation for Pynq". I tried to search the key-words in the whole "TVM" project but find nothing. Then I find object **self.fpga_freq** and **self.fpga_per in** in `pkg_config.py` file, but it seems noting changed between new bitstream generated with "142MHz" and "6ns" and old bitstream. 2.I notice vta architecture have some "knobs" which provide users to adjust VTA in **GEMM hardware intrinsic shape**, **numbers of parallel arithmetic units in the tensor ALU**, **BRAM distribution bwteen on-chip memories**… Are these "knobs" those listed in the `vta_config.json` file? What is their correspondence? If not, where can I config them? I'll be very appreciate if someone being able to get me through these problem. Thanks a lot. --- [Visit Topic](https://discuss.tvm.apache.org/t/vta-generate-a-new-bitstream-for-other-targets-and-clk-frequency/8500/1) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/6813218619818b2f424665b771191d85cfbd575bff2a4c927092f19b353b91ab).
