http://igoro.com/archive/volatile-keyword-in-c-memory-model-explained/As I understand, because Itanium doesn't have cache coherency, a memory fence is needed to implement volatile load and store. On x86 load and store are already volatile because of cache coherency, so fences are not needed.
- shared methods unknown soldier
- Re: shared methods Benjamin Thaut
- Re: shared methods unknown soldier
- Re: shared methods Kagamin
- Re: shared methods Johannes Pfau
- Re: shared methods Kagamin
- Re: shared methods Kagamin
- Re: shared methods Johannes Pfau
- Re: shared methods Kagamin
- Re: shared methods Johannes Pfau
- Re: shared methods Kagamin
- Re: shared methods Johannes Pfau
- Re: shared methods Kagamin
