>>>>> "Sathya" == Sathya Narayanan N <[email protected]> writes:
Sathya> Hi Peter, Sathya> Thanks. I am trying to port it to a RISCV running FPGA and Sathya> show the output through UART ? Is it possible with just the Sathya> upstreamed code or something I need to do ? If there is a proxy-kernel that handles the UART on your FPGA then I'd expect the upstream code to work. But as I said, we haven't tried this yet. Peter C -- Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/ Trustworthy Systems Group Data61, CSIRO (formerly NICTA) _______________________________________________ Devel mailing list [email protected] https://sel4.systems/lists/listinfo/devel
