> I'm Hesham ALMatary a computer science research student at the > University of York. I am considering porting L4 microkernel variants > to RISC-V [2] (for both my research and Google Summer of Code), and > Fiasco.OC is one of these variants, but I want to extend the options > here by asking about seL4. > > Is this project would be: first applicable, and second of interest to > you? And if yes, would you offer some help (guidance)? I am sending > this message as suggested here [1] that I should contact you if I'm > willing to port seL4 to a new platform.
An architecture port is a bit of a bigger beast than a platform port ;-) I haven’t looked at RISC-V in detail, so don’t know what would be involved. But, generally speaking, a performant ISA port requires a good understanding of both kernel design and implementation as well as architecture. We’re obviously interested in seeing seL4 used as widely as possible, and believe (with support of some solid facts) that seL4 is the leading microkernel that defines the state of the art. It is also much simpler than Fiasco.OC (about 1/3 of the SLOC size). We’ll be happy to provide guidance (on the usual best-effort basis). Gernot ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments. _______________________________________________ Devel mailing list [email protected] https://sel4.systems/lists/listinfo/devel
