e...@thyrsus.com said: > Thanks, I'll read those. Actually, re-read the first and read the second.
The PID page has a lot of non-math explanations. It might work better to scan it first. As background technology in this area, there are also DLLs - delay locked loops. Some FPGAs use them instead of PLLs. It avoids analog logic at the cost of digital logic and digital logic is what FPGAs are good at. What you want is a negative delay to undo collected delays in the system. With a periodic signal (aka clock) you can get a delay of -x by delaying a whole cycle less x. You can get a long delay with a chain of buffers and a multiplexer to select the right tap. Delay-locked loop https://en.wikipedia.org/wiki/Delay-locked_loop -- These are my opinions. I hate spam. _______________________________________________ devel mailing list devel@ntpsec.org http://lists.ntpsec.org/mailman/listinfo/devel
