A vendor-independent x86-64 psABI
supplement defines four "microachitecture levels": `x86-64-v1` (the
baseline, our code targets this), `x86-64-v2` (+`SSE3`, CentoOS
targets this), `x86-64-v3` (+`AVX`), `x86-64-v4` (+`AVX512`) [1].
The levels are not explicit about the classification of a CPU that has
AVX (128-bit xmm registers) but lacks AVX2 (256-bit ymm registers.)
For instance:
cpu family : 21
model : 16
model name : AMD A10-5800K APU with Radeon(tm) HD Graphics
and
cpu family : 21
model : 56
model name : AMD A10-7890K Radeon R7, 12 Compute Cores 4C+8G
Both have sse, sse2, ssse3, sse4_1, sse4_2, sse4a, popcnt, aes,
pclmulqdq, and bmi1; so both satisfy floating-point arithmetic and
[scalar] crypto requirements. (More details at
https://discussion.fedoraproject.org/t/f42-change-proposal-optimized-binaries-for-the-amd64-x86-64-architecture-v2-self-contained/142032/4
]
The proposal should be revised to consider this case explicitly.
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