W dniu 7.11.2024 o 13:04, Jonathan Cameron pisze:
On Tue, 5 Nov 2024 18:43:46 +0800
"Yuquan Wang"<wangyuquan1...@phytium.com.cn> wrote:
This creates a default pxb-cxl (bus_nr=0xc0) bridge with two
cxl root ports on sbsa-ref. And the memory layout places 64K
space for the cxl host bridge register regions(CHBCR) in the
sbsa-ref memmap.
In addition, this support indepentent mmio32(32M) & mmio64(1M)
space for cxl components.
Those are too small. Might work today but not sustainable.
I'm a bit surprised it was this simple to move the MMIO Space away
from what is normally done for PXBs.
I think it might work because the GPEX memory windows are effectively
unlimited in size but I'd like some more eyes on this from people
familiar with how all that works and whether there might be some
corner cases that you haven't seen yet.
I see the same problem as with multiple PCIe buses (for NUMA systems):
pci 0000:c0:00.0: bridge window [io size 0x1000]: can't assign; no space
pci 0000:c0:00.0: bridge window [io size 0x1000]: failed to assign
pci 0000:c0:01.0: bridge window [io size 0x1000]: can't assign; no space
pci 0000:c0:01.0: bridge window [io size 0x1000]: failed to assign
I do not know how it looks on real hardware (all my systems have one
PCIe bus) but shouldn't each host bridge have own separate resource
windows for config space, buses, mmio etc.?
Now we squeeze all pcie buses as pcie-pxb devices and this patch adds
cxl to the combo.
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