On Fri, 30 Aug 2024 11:15:44 +0800
Yuquan Wang <wangyuquan1...@phytium.com.cn> wrote:
> This adds relevant definitions and descriptions of acpi0016 and
> acpi0017 to support CXL.
>
> With the implementation of pxb-cxl on the original pcie host bridge,
> the previous space layout of mmio32 & mmio64 have to be divided to
> provide the mmio space for cxl host bridge.
>
> I'm not sure if the new space layout would bring a series of bad
> influence, but it seems that the base address and size of cxl host
> bridge is ok.
>
> Signed-off-by: Yuquan Wang <wangyuquan1...@phytium.com.cn>
I'll go as far as saying this looks about right to me, but needs
some more eyes to be more certain.
Trivial comments inline.
Jonathan
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> index c134fb66e860..94d0b2cbb118 100644
> --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> @@ -483,5 +849,45 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
> }
> } // End _OSC
> }
> +
> + Scope (\_SB)
> + {
> + // CXL Root for OS Driver
> + Device (CXLM)
> + {
> + Name (_HID, "ACPI0017") // _HID: Hardware ID
> + Method (_STA, 0, NotSerialized) // _STA: Status
> + {
> + Return (0x0B)
> + }
> +
> + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
> + {
> + If ((Arg0 == ToUUID ("f365f9a6-a7de-4071-a66a-b40c0b4f8e52")
> /* Unknown UUID */))
Name that UUID in the comment. I was thinking you didn't have QTG querying
supported
because oddly I can't remember the uuid :)
> + {
> + If ((Arg2 == Zero))
> + {
> + Return (Buffer (One)
> + {
> + 0x01 //
> .
> + })
> + }
> +
> + If ((Arg2 == One))
> + {
> + Return (Package (0x02)
> + {
> + One,
> + Package (0x02)
> + {
> + Zero,
> + One
Hmm. I probably have this wrong in the qemu code, but it should be safe.
This is saying QTG 0 default with fallback to 1. We don't have anything
in group 1.
Ah well never mind.
> + }
> + })
> + }
> + }
> + }
> + }
> + }
> } // Scope (_SB)
> }
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