On Wed, Jul 10, 2024 at 14:58:52 +0100, Jonathan Cameron wrote:
> On Tue, 9 Jul 2024 14:01:53 +0100
> "Leif Lindholm" <quic_llind...@quicinc.com> wrote:
>
> > On Tue, Jul 09, 2024 at 12:47:09 +0200, Marcin Juszkiewicz wrote:
> > > During Linaro Connect MAD24 I was asked to move cache information from
> > > being 'per cluster' to be 'per core'. This is a move for implementing
> > > MPAM support.
> > >
> > > So topology moves from:
> > >
> > > Socket -> Clusters -> Cores + Caches -> Threads (if exist)
> > >
> > > to:
> > >
> > > Socket -> Clusters -> Cores -> Caches + Threads (if exist)
> > >
> > > Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
> > > implement them at all so we can tell whatever.
>
> They should match the system registers.
> CCSIDR etc which are provided by QEMU.
That's a good point. Thanks for bringing that up.
edk2-platforms/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c
demonstrates how this can be done with existing edk2 interfaces and
definitions.
Ultimately, this will only ever be possible to runtime-generate in
edk2 for homogenous systems. Any big-little type setups need to get
the information from TF-A.
/
Leif
> Here's some old code for doing PPTT cache entry generation for arm-virt.
>
> https://lore.kernel.org/qemu-devel/20230808115713.2613-2-jonathan.came...@huawei.com/
>
> The numbers might happen to match what it has for the cpu you are using
> though.
> https://elixir.bootlin.com/qemu/latest/source/target/arm/tcg/cpu64.c#L1051
>
> For n2 that looks to be 64+64+512...
>
>
>
> > >
> > > Signed-off-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
> >
> > Reviewed-by: Leif Lindholm <quic_llind...@quicinc.com>
> >
> > /
> > Leif
> >
> > > ---
> > > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 47
> > > +++++++++++---------
> > > 1 file changed, 25 insertions(+), 22 deletions(-)
> > >
> > > diff --git
> > > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > index cf0102d11f1f..a7a9664abdcb 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > > @@ -562,8 +562,8 @@ AddPpttTable (
> > > TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
> > > CpuTopo.Sockets * (sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > > CpuTopo.Clusters * (sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > > - sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> > > CpuTopo.Cores *
> > > (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > > +
> > > sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
> > >
> > > sizeof (UINT32) * 2)));
> > >
> > > if (CpuTopo.Threads > 1) {
> > > @@ -609,10 +609,7 @@ AddPpttTable (
> > >
> > > ClusterIndex = SocketIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > > for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
> > > - L1DCacheIndex = ClusterIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > > - L1ICacheIndex = L1DCacheIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > - L2CacheIndex = L1ICacheIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > - CoreIndex = L2CacheIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > + CoreIndex = ClusterIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > >
> > > // Add the Cluster PPTT structure
> > > EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster =
> > > SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
> > > @@ -624,27 +621,15 @@ AddPpttTable (
> > > CopyMem (New, &Cluster, sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
> > > New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
> > >
> > > - // Add L1 D Cache structure
> > > - L1DCache.CacheId = CacheId++;
> > > - CopyMem (New, &L1DCache, sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =
> > > L2CacheIndex;
> > > - New +=
> > > sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > -
> > > - // Add L1 I Cache structure
> > > - L1ICache.CacheId = CacheId++;
> > > - CopyMem (New, &L1ICache, sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =
> > > L2CacheIndex;
> > > - New +=
> > > sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > -
> > > - // Add L2 Cache structure
> > > - L2Cache.CacheId = CacheId++;
> > > - CopyMem (New, &L2Cache, sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > -
> > > for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
> > > UINT32 *PrivateResourcePtr;
> > > UINT32 CoreCpuId;
> > >
> > > + // two UINT32s for PrivateResourcePtr data
> > > + L1DCacheIndex = CoreIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
> > > + L1ICacheIndex = L1DCacheIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > + L2CacheIndex = L1ICacheIndex + sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > if (CpuTopo.Threads == 1) {
> > > CoreCpuId = CpuId;
> > > } else {
> > > @@ -665,6 +650,23 @@ AddPpttTable (
> > > PrivateResourcePtr[1] = L1ICacheIndex;
> > > New += (2 * sizeof (UINT32));
> > >
> > > + // Add L1 D Cache structure
> > > + L1DCache.CacheId = CacheId++;
> > > + CopyMem (New, &L1DCache, sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =
> > > L2CacheIndex;
> > > + New +=
> > > sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > + // Add L1 I Cache structure
> > > + L1ICache.CacheId = CacheId++;
> > > + CopyMem (New, &L1ICache, sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache =
> > > L2CacheIndex;
> > > + New +=
> > > sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > + // Add L2 Cache structure
> > > + L2Cache.CacheId = CacheId++;
> > > + CopyMem (New, &L2Cache, sizeof
> > > (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
> > > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
> > > +
> > > if (CpuTopo.Threads == 1) {
> > > CpuId++;
> > > } else {
> > > @@ -685,6 +687,7 @@ AddPpttTable (
> > > }
> > >
> > > CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
> > > sizeof (UINT32) * 2;
> > > + CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
> > > }
> > >
> > > ClusterIndex = CoreIndex;
> > >
> > > --
> > > 2.45.2
> > >
> >
> >
> >
> >
> >
>
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119867): https://edk2.groups.io/g/devel/message/119867
Mute This Topic: https://groups.io/mt/107120146/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
