REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4745
This commit fixes the issue reported in the BZ4745.
The wrmsr was always writing 0 to the higher 32 bits of the msr register.
This was due to a logical flaw in the code, where the input variable of
type unsigned int was left shitted by 32 bits without explicitly
converting it to a 64 bit value.
The issue is with the below statement.
data = vedx << 32 | veax;
Where the vedx which is an unsigned int, after left shifting by 32 bits
its value will be set to 0. Because of this the higher 32 bits of the MSR
are always set to 0. This has been fixed by this commit.
Cc: Rebecca Cran <rebe...@bsdio.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Jayaprakash N <n.jayaprak...@intel.com>
Signed-off-by: Jayaprakash N <n.jayaprak...@intel.com>
---
.../Python/Python-3.6.8/PyMod-3.6.8/Modules/edk2module.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/edk2module.c
b/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/edk2module.c
index 8786df8..06bcf82 100644
--- a/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/edk2module.c
+++ b/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/edk2module.c
@@ -3886,7 +3886,8 @@ edk2_wrmsr(PyObject *self, PyObject *args)
UINT64 data = 0;
if (!PyArg_ParseTuple(args, "III", &vecx, &veax, &vedx))
return NULL;
- data = vedx << 32 | veax;
+ data = LShiftU64(vedx, 32);
+ data = BitFieldOr64(data, 0, 31, veax);
Py_BEGIN_ALLOW_THREADS
AsmWriteMsr64(vecx, data);
Py_END_ALLOW_THREADS
--
2.44.0.windows.1
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