This change looks good. Reviewed-by: Liming Gao <gaolim...@byosoft.com.cn>
Cheng and Hao: Have you any comments for this patch? Thanks Liming > -----邮件原件----- > 发件人: Dat Mach <dm...@nvidia.com> > 发送时间: 2024年2月26日 10:00 > 收件人: devel@edk2.groups.io > 抄送: gao.ch...@intel.com; hao.a...@intel.com; ray...@intel.com; > gaolim...@byosoft.com.cn; Dat Mach <dm...@nvidia.com> > 主题: [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB > address translation > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560 > > Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the > DXE_ASSERT > caused by the TRB size round up from 16 to 64 for most cases. > > However, there is a remaining case that the TRB size is also rounded up > during setting TR dequeue pointer that would trigger DXE_ASSERT. > > This patch sets the alignment flag to FALSE in XhcSetTrDequeuePointer > to fix this issue as well. > > Signed-off-by: Dat Mach <dm...@nvidia.com> > --- > MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 2 +- > MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > index 05528a478b..5d735008ba 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > @@ -3539,7 +3539,7 @@ XhcSetTrDequeuePointer ( > // Send stop endpoint command to transit Endpoint from running to stop > state > // > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); > - PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); > + PhyAddr = UsbHcGetPciAddrForHostAddr > (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof > (CMD_SET_TR_DEQ_POINTER), FALSE); > CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | > Urb->Ring->RingPCS; > CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr); > CmdSetTRDeq.CycleBit = 1; > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > index 53272f62dd..c956e45907 100644 > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > @@ -2526,7 +2526,7 @@ XhcPeiSetTrDequeuePointer ( > // Send stop endpoint command to transit Endpoint from running to stop > state > // > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); > - PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); > + PhyAddr = UsbHcGetPciAddrForHostAddr > (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof > (CMD_SET_TR_DEQ_POINTER), FALSE); > CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | > Urb->Ring->RingPCS; > CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr); > CmdSetTRDeq.CycleBit = 1; > -- > 2.44.0.rc2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116347): https://edk2.groups.io/g/devel/message/116347 Mute This Topic: https://groups.io/mt/104735560/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
