From bfe08a688b9074b507e962982f373f88fa16ac5a Mon Sep 17 00:00:00 2001
From: vicshuang <vicshuang@tencent.com>
Date: Fri, 1 Mar 2024 16:30:53 +0800
Subject: [PATCH] fix:Fixed incorrect Timer timing in RISC-V The current code
 has the problem of inaccurate Timer timing. The main reason is that the
 PcdCpuCoreCrystalClockFrequency variable required by the
 BaseRiscV64CpuTimerLib.inf library used by the system is not assigned a value
 in the file.

    Signed-off-by: Song Huang  <vicshuang@tencent.com>
                   Bin Fan <tombinfan@tencent.com>
                   Lingheng Du <dylanlhdu@tencent.com>
---
 .../U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc  | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
index 404c0b71ca..d7115f3eba 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
@@ -3,6 +3,8 @@
 #
 #  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
+#  Copyright (c) 2024, Tencent. All rights reserved.<BR>
+#
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -87,7 +89,7 @@ SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize   = $(SCRATCH_SIZE)
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase = $(CODE_BASE_ADDRESS) + $(FW_SIZE)
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000
 
-
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency    = 1000000
 SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz    = 1000000
 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock = 1000000000 # 1GHz system clock
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId                  = 1          # Boot hart ID
-- 
2.34.1