On Thu, Feb 22, 2024 at 11:30:01AM -0600, Tom Lendacky wrote: > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 > > The SVSM specification documents an alternative method of discovery for > the SVSM using a reserved CPUID bit and a reserved MSR. > > For the CPUID support, the #VC handler of an SEV-SNP guest should modify > the returned value in the EAX register for the 0x8000001f CPUID function > by setting bit 28 when an SVSM is present. > > For the MSR support, new reserved MSR 0xc001f000 has been defined. A #VC > should be generated when accessing this MSR. The #VC handler is expected > to ignore writes to this MSR and return the physical calling area address > (CAA) on reads of this MSR. > > Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
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