On Tuesday, February 20, 2024 5:07 PM, Gerd Hoffmann wrote:
> Subject: [PATCH v3 0/6] OvmfPkg: Add support for 5-level paging
> 
> Patch #1 + #2 fix MdeModulePkg/DxeIplPeim to not assert in case a 5-level
> enabled build runs in 4-level paging mode.
> 
> Patch #2 - #4 update OvmfPkg ResetVector, adding support for 5-level paging
> (setup 5-level page tables in case both la57 and gigabyte pages are supported
> by the vCPU).
> 
> Patch #5 updates PlatformInitLib for 5-level paging support (update PhysBits
> calculation).
> 
> Known issues / limitations:
>  - BaseMemEncryptSevLib must be updated to also support 5-level
>    paging for full 5-level paging support in SEV mode.
> 
> The patch series does *not* enable 5-level paging by default.
> Building with 5-level paging support can be done by compiling OVMF with '--
> pcd PcdUse5LevelPageTable=TRUE'.
> 
> v3:
>  - add resetvector fixes for sev and tdx
> v2 changes:
>  - fix sev/tdx handling with 5-level paging.
>  - more comments for 5-level page table setup.
>  - improve PAGE_* naming (new patch #3).
>  - rename Page5LevelSupported to Page5LevelEnabled (new patch #2).
>  - pick up some review tags.
> 
> Gerd Hoffmann (6):
>   MdeModulePkg/DxeIplPeim: fix PcdUse5LevelPageTable assert
>   MdeModulePkg/DxeIplPeim: rename variable
>   OvmfPkg/ResetVector: improve page table flag names
>   OvmfPkg/ResetVector: SEV: keep #vc handler installed longer
>   OvmfPkg/ResetVector: add 5-level paging support
>   OvmfPkg/PlatformInitLib: add 5-level paging support
> 
>  OvmfPkg/ResetVector/ResetVector.inf           |   1 +
>  .../Core/DxeIplPeim/X64/VirtualMemory.c       |  24 +--
>  OvmfPkg/Library/PlatformInitLib/MemDetect.c   |  57 ++++--
>  OvmfPkg/ResetVector/Ia32/AmdSev.asm           |   7 +-
>  OvmfPkg/ResetVector/Ia32/IntelTdx.asm         |  17 +-
>  OvmfPkg/ResetVector/Ia32/PageTables64.asm     | 170 +++++++++++++++---
>  OvmfPkg/ResetVector/ResetVector.nasmb         |   1 +
>  7 files changed, 224 insertions(+), 53 deletions(-)
> 

Test the patch-set in TDX (OvmfPkgX64 and Intel/IntelTdx) and both passed.

Tested-by: Min Xu <min.m...@intel.com>


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