From: Duke Zhai <duke.z...@amd.com>
BZ #:4640
In V2: Improve coding style.
1.Remove the leading underscore and use double underscore at trailing in C
header files.
2.Remove old tianocore licenses and redundant license description.
3.Improve coding style. For example: remove space between @param.
In V1:
Chachani board jump to PlatformSec function after x86 releasing.
This module provides the SEC entry function, which does platform-related
early initialization.
Signed-off-by: Ken Yao <ken....@amd.com>
Cc: Duke Zhai <duke.z...@amd.com>
Cc: Eric Xing <eric.x...@amd.com>
Cc: Igniculus Fu <igniculus...@amd.com>
Cc: Abner Chang <abner.ch...@amd.com>
---
.../Library/PlatformSecLib/Ia32/Flat32.nasm | 534 ++++++++++++++++++
.../Library/PlatformSecLib/Ia32/Platform.inc | 53 ++
.../Library/PlatformSecLib/PlatformSecLib.c | 196 +++++++
.../Library/PlatformSecLib/PlatformSecLib.inf | 61 ++
.../PlatformSecLib/PlatformSecLibModStrs.uni | 19 +
5 files changed, 863 insertions(+)
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.c
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf
create mode 100644
Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
new file mode 100644
index 0000000000..5638c411e3
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm
@@ -0,0 +1,534 @@
+;/** @file
+; AMD VanGoghBoard PlatformSecLib
+; This is the code that goes from real-mode to protected mode.
+; It consumes the reset vector, configures the stack.
+;
+; Copyright (c) 2013-2015 Intel Corporation. All rights reserved.<BR>
+; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;**/
+
+;
+; Include processor definitions
+;
+%use masm
+
+
+%include "Platform.inc"
+
+;
+; CR0 cache control bit definition
+;
+CR0_CACHE_DISABLE EQU 040000000h
+CR0_NO_WRITE EQU 020000000h
+BSP_STACK_BASE_ADDR EQU FixedPcdGet32
(PcdPeiCorePeiPreMemoryStackBaseAddress) ; Base address for core 0 stack
+PRE_MEM_STACK_SIZE EQU FixedPcdGet32 (PcdPeiCorePeiPreMemoryStackSize)
+PCIEX_LENGTH_BIT_SETTING EQU 011000b
+
+MSR_IA32_EFER EQU 0c0000080h ; Extended Feature Enable
Register
+MSR_IA32_EFER_LME EQU 8 ; Long Mode Enable
+
+MSR_SMM_BASE EQU 0c0010111h ; SMBASE Register
+
+SMM_BASE_DEFAULT EQU 30000h ; reset value of MSR MSR_SMM_BASE
+
+SMMMASK_ADDRESS EQU 0c0010113h ; SMM TSeg Base Address
+SMMMASK_ADDRESS_AE EQU 0 ; Aseg Address Range Enable
+SMMMASK_ADDRESS_TE EQU 1 ; Tseg Address Range Enable
+
+;
+; In Modified Conventional Resume S3 Design:
+; With Modified Conventional Resume path, the x86 resumes from sleep,
+; begins executing code from a predefined SMM resume vector and then
+; jump to ROM code to continue conventional resume.
+; EDX is filled with special signature "0x55AABB66" when jump to Sec,
+; this signature can be used to identify if resume back from SMM resume.
+;
+SMM_RESUME_SIGNATURE EQU 055AABB66h
+
+PCAT_RTC_ADDRESS_REGISTER EQU 0x70
+PCAT_RTC_DATA_REGISTER EQU 0x71
+
+NMI_DISABLE_BIT EQU 0x80
+
+RTC_ADDRESS_REGISTER_A EQU 0x0A ; R/W[0..6] R0[7]
+RTC_ADDRESS_REGISTER_B EQU 0x0B ; R/W
+RTC_ADDRESS_REGISTER_C EQU 0x0C ; RO
+RTC_ADDRESS_REGISTER_D EQU 0x0D ; R/W
+
+;
+; External and public declarations
+; TopOfStack is used by C code
+; SecStartup is the entry point to the C code
+; Neither of these names can be modified without
+; updating the C code.
+;
+extern ASM_PFX(SecStartup)
+
+SECTION .text
+;
+; Protected mode portion initializes stack, configures cache, and calls C
entry point
+;
+
+;----------------------------------------------------------------------------
+;
+; Procedure: ProtectedModeEntryPoint
+;
+; Input: Executing in 32 Bit Protected (flat) mode
+; cs: 0-4GB
+; ds: 0-4GB
+; es: 0-4GB
+; fs: 0-4GB
+; gs: 0-4GB
+; ss: 0-4GB
+;
+; Output: This function never returns
+;
+; Destroys:
+; ecx
+; edi
+; esi
+; esp
+;
+; Description:
+; Perform any essential early platform initilaisation
+; Setup a stack
+; Call the main EDKII Sec C code
+;
+;----------------------------------------------------------------------------
+
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+ ;
+ ; Check if system resumes from S3 SMM mode, if yes, continue to use S3
preserved stack setting
+ ;
+ cmp edi, SMM_RESUME_SIGNATURE
+ je S3_SecRoutine
+
+ JMP32 ASM_PFX(stackless_EarlyPlatformInit)
+ mov esp, BSP_STACK_BASE_ADDR+PRE_MEM_STACK_SIZE
+
+ ;
+ ; Push processor count to stack first, then BIST status (AP then BSP)
+ ;
+ mov eax, 1
+ cpuid
+ shr ebx, 16
+ and ebx, 0000000FFh
+ cmp bl, 1
+ jae PushProcessorCount
+
+ ;
+ ; Some processors report 0 logical processors. Effectively 0 = 1.
+ ; So we fix up the processor count
+ ;
+ inc ebx
+
+PushProcessorCount:
+ push ebx
+
+ movd eax, mm0 ; BIST saved in mm0 at reset vector.
+ ;
+ ; We need to implement a long-term solution for BIST capture. For now, we
just copy BSP BIST
+ ; for all processor threads
+ ;
+ mov ecx, ebx
+PushBist:
+ push eax
+ loop PushBist
+
+ ;Clear Long Mode Enable
+ mov ecx, MSR_IA32_EFER
+ rdmsr
+ btr eax, MSR_IA32_EFER_LME ; Set LME=0
+ wrmsr
+
+ ;Open smm ram
+ mov ecx, SMMMASK_ADDRESS
+ rdmsr
+ btr eax, SMMMASK_ADDRESS_AE ; Set AValid=0
+ btr eax, SMMMASK_ADDRESS_TE ; Set TValid=0
+ wrmsr
+
+ ;Rebase SMRAM Base Address to power on default value
+ mov ecx, MSR_SMM_BASE
+ rdmsr
+ mov eax, SMM_BASE_DEFAULT
+ wrmsr
+
+ mov ecx, APIC_BASE_ADDRESS
+ rdmsr
+ bt eax, APIC_BSC ; Is this the BSC?
+ jc IsBsp
+
+IsAp:
+ cli ; Family 17h AP just halt here
+ hlt
+ jmp IsAp
+
+IsBsp:
+ push ebp ; BFV base address
+ ;
+ ; Pass stack base into the PEI Core
+ ;
+ push BSP_STACK_BASE_ADDR
+
+ ;
+ ; Pass stack size into the PEI Core
+ ;
+ push PRE_MEM_STACK_SIZE
+ ;
+ ; Pass Control into the PEI Core
+ ;
+ ; UefiCpuPkg\SecCore\SecMain.c:
+ ;
+ ; VOID
+ ; EFIAPI
+ ; SecStartup (
+ ; IN UINT32 SizeOfRam,
+ ; IN UINT32 TempRamBase,
+ ; IN VOID *BootFirmwareVolume
+ ; );
+ call ASM_PFX(SecStartup)
+
+ ;
+ ; Sec Core should never return to here, this is just to capture an invalid
return.
+ ;
+ jmp $
+
+S3_SecRoutine:
+ ;Clear Long Mode Enable
+ mov ecx, MSR_IA32_EFER
+ rdmsr
+ btr eax, MSR_IA32_EFER_LME ; Set LME=0
+ wrmsr
+
+ ;Open smm ram
+ mov ecx, SMMMASK_ADDRESS
+ rdmsr
+ btr eax, SMMMASK_ADDRESS_AE ; Set AValid=0
+ btr eax, SMMMASK_ADDRESS_TE ; Set TValid=0
+ wrmsr
+
+ ;Rebase SMRAM Base Address to power on default value
+ mov ecx, MSR_SMM_BASE
+ rdmsr
+ mov eax, SMM_BASE_DEFAULT
+ wrmsr
+
+ mov ecx, APIC_BASE_ADDRESS
+ rdmsr
+ bt eax, APIC_BSC ; Is this the BSC?
+ jc IsBspInS3
+
+IsApInS3:
+ cli ; Family 17h AP just halt here
+ hlt
+ jmp IsApInS3
+
+IsBspInS3:
+
+ ;;
+ ;; Enable eSPI port 80 and FCH UART2 during S3 resume start
+ ;;
+ push eax
+ push ebx
+ push ecx
+ push edx
+ push esi
+ push edi
+
+ mov eax, FixedPcdGet64 (PcdPciExpressBaseAddress)
+ or eax, (PCIEX_LENGTH_BIT_SETTING | 1)
+ xor edx, edx
+ mov ecx, 0C0010058h
+ wrmsr
+
+ ;
+ ; Enable port 80 decode to eSPI ;
+ ;
+ mov ebx, FixedPcdGet64 (PcdPciExpressBaseAddress) | (LPC_PFA << 12) |
LPC_SPI_BASE_ADDR ; PCI Configuration address
+ mov ebx, dword ptr [ebx]
+ and ebx, 0xFFFFFF00
+ add ebx, 0x10000 ; Get the eSPI base address
+ add ebx, ESPI_SLAVE0_DECODE_EN
+ mov eax, dword ptr [ebx]
+ or eax, ESPI_SLAVE0_DECODE_EN_IO_80_EN
+ mov dword ptr [ebx], eax
+
+ ;
+ ; Program IOMUX for eSPI port 80, GPIO 30 and 31 to function 1
+ ;
+ mov ebx, 0xFED80D1E
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ mov ebx, 0xFED80D1F
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ mov al, 0x33
+ out 0x80, al
+
+ ;
+ ; Program IOMUX for FCH UART2, GPIO 136 and 138 to function 1
+ ;
+ mov ebx, 0xFED80D88
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ mov ebx, 0xFED80D8A
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ pop edi
+ pop esi
+ pop edx
+ pop ecx
+ pop ebx
+ pop eax
+ ;;
+ ;; Enable eSPI port 80 and FCH UART2 during S3 resume end
+ ;;
+
+ pop ebx
+ mov edi, ebx
+
+ pop ebx
+ mov esi, ebx
+
+ pop edx
+ pop eax
+
+ pop ebx
+ mov esp, ebx
+
+ push 1 ; set Processor Count to 1 for S3 resume path which is not used
finally.
+ push 0 ; set BIST to 0
+
+ push ebp ; BFV base address
+
+ ;
+ ; Pass stack base into the PEI Core
+ ;
+ sub ebx, PRE_MEM_STACK_SIZE
+ push ebx
+
+ ;
+ ; Pass stack size into the PEI Core
+ ;
+ push PRE_MEM_STACK_SIZE
+
+ ;
+ ; Pass Control into the PEI Core
+ ;
+ call ASM_PFX(SecStartup)
+
+ ;
+ ; Sec Core should never return to here, this is just to capture an invalid
return.
+ ;
+ jmp $
+
+;----------------------------------------------------------------------------
+;
+; Procedure: stackless_EarlyPlatformInit
+;
+; Input: esp - Return address
+;
+; Output: None
+;
+; Destroys:
+; eax
+; ecx
+; dx
+; ebp
+;
+; Description:
+; Any essential early platform initialisation required:
+; (1) Setup PCIEXBAR access mechanism
+; (2) enable IO port 80 to eSPI
+;
+;----------------------------------------------------------------------------
+global ASM_PFX(stackless_EarlyPlatformInit)
+ASM_PFX(stackless_EarlyPlatformInit):
+
+ ;
+ ;PcRtcInit start
+ ;
+ ;;
+ ;; Initialize RTC Register
+ ;;
+ ;; Make sure Division Chain is properly configured,
+ ;; or RTC clock won't "tick" -- time won't increment
+ ;;
+ in al, PCAT_RTC_ADDRESS_REGISTER
+
+ mov al, RTC_ADDRESS_REGISTER_A | NMI_DISABLE_BIT
+ out PCAT_RTC_ADDRESS_REGISTER, al
+
+ mov al, FixedPcdGet8 (PcdInitialValueRtcRegisterA)
+ out PCAT_RTC_DATA_REGISTER, al
+
+
+ ;;
+ ;; Read Register B
+ ;;
+ in al, PCAT_RTC_ADDRESS_REGISTER
+
+ mov al, RTC_ADDRESS_REGISTER_B | NMI_DISABLE_BIT
+ out PCAT_RTC_ADDRESS_REGISTER, al
+
+ in al, PCAT_RTC_DATA_REGISTER
+
+
+ ;;
+ ;; Clear RTC flag register
+ ;;
+ in al, PCAT_RTC_ADDRESS_REGISTER
+
+ mov al, RTC_ADDRESS_REGISTER_C | NMI_DISABLE_BIT
+ out PCAT_RTC_ADDRESS_REGISTER, al
+
+ in al, PCAT_RTC_DATA_REGISTER
+
+
+ ;;
+ ;; Clear RTC register D
+ ;;
+ in al, PCAT_RTC_ADDRESS_REGISTER
+
+ mov al, RTC_ADDRESS_REGISTER_D | NMI_DISABLE_BIT
+ out PCAT_RTC_ADDRESS_REGISTER, al
+
+ mov al, FixedPcdGet8 (PcdInitialValueRtcRegisterD)
+ out PCAT_RTC_DATA_REGISTER, al
+ ;
+ ;PcRtcInit end
+ ;
+
+ mov eax, FixedPcdGet64 (PcdPciExpressBaseAddress)
+ or eax, (PCIEX_LENGTH_BIT_SETTING | 1)
+ xor edx, edx
+ mov ecx, 0C0010058h
+ wrmsr
+
+ ;
+ ; Enable port 80 decode to eSPI ;
+ ;
+ mov ebx, FixedPcdGet64 (PcdPciExpressBaseAddress) | (LPC_PFA << 12) |
LPC_SPI_BASE_ADDR ; PCI Configuration address
+ mov ebx, dword ptr [ebx]
+ and ebx, 0xFFFFFF00
+ add ebx, 0x10000 ; Get the eSPI base address
+ add ebx, ESPI_SLAVE0_DECODE_EN
+ mov eax, dword ptr [ebx]
+ or eax, ESPI_SLAVE0_DECODE_EN_IO_80_EN
+ mov dword ptr [ebx], eax
+
+ ;
+ ; Program IOMUX for eSPI port 80, GPIO 30 and 31 to function 1
+ ;
+ mov ebx, 0xFED80D1E
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ mov ebx, 0xFED80D1F
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ mov al, 0x88
+ out 0x80, al
+
+
+ ;
+ ; Program IOMUX for FCH UART2, GPIO 136 and 138 to function 1
+ ;
+ mov ebx, 0xFED80D88
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ mov ebx, 0xFED80D8A
+ mov eax, dword ptr [ebx]
+ or eax, 1
+ mov dword ptr [ebx], eax
+
+ RET32
+
+;----------------------------------------------------------------------------
+;
+; Procedure: stackless_PCIConfig_Write
+;
+; Input: esp - return address
+; eax - Data to write
+; ebx - PCI Config Address
+;
+; Output: None
+;
+; Destroys:
+; dx
+;
+; Description:
+; Perform a DWORD PCI Configuration write
+;
+;----------------------------------------------------------------------------
+global ASM_PFX(stackless_PCIConfig_Write)
+ASM_PFX(stackless_PCIConfig_Write):
+
+ ;
+ ; Write the PCI Config Address to the address port
+ ;
+ xchg eax, ebx
+ mov dx, PCI_ADDRESS_PORT
+ out dx, eax
+ xchg eax, ebx
+
+ ;
+ ; Write the PCI DWORD Data to the data port
+ ;
+ mov dx, PCI_DATA_PORT
+ out dx, eax
+
+ RET32
+
+
+;----------------------------------------------------------------------------
+;
+; Procedure: stackless_PCIConfig_Read
+;
+; Input: esp - return address
+; ebx - PCI Config Address
+;
+; Output: eax - Data read
+;
+; Destroys:
+; eax
+; dx
+;
+; Description:
+; Perform a DWORD PCI Configuration read
+;
+;----------------------------------------------------------------------------
+global ASM_PFX(stackless_PCIConfig_Read)
+ASM_PFX(stackless_PCIConfig_Read):
+ ;
+ ; Write the PCI Config Address to the address port
+ ;
+ xchg eax, ebx
+ mov dx, PCI_ADDRESS_PORT
+ out dx, eax
+ xchg eax, ebx
+
+ ;
+ ; Read the PCI DWORD Data from the data port
+ ;
+ mov dx, PCI_DATA_PORT
+ in eax, dx
+
+ RET32
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc
new file mode 100644
index 0000000000..7ef0d9a2c0
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc
@@ -0,0 +1,53 @@
+;/** @file
+; AMD VanGoghBoard PlatformSecLib
+; Platform Specific Definitions
+;
+; Copyright (c) 2013-2015 Intel Corporation. All rights reserved.<BR>
+; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;**/
+
+%macro JMP32 1
+ lea esp, %%target
+ jmp %1
+%%target:
+%endmacro
+
+%macro RET32 0
+ jmp esp
+%endmacro
+
+;
+; RTC/CMOS definitions
+;
+RTC_INDEX EQU 070h
+ NMI_DISABLE EQU 080h ; Bit7=1 disables NMI
+ NMI_ENABLE EQU 000h ; Bit7=0 disables NMI
+RTC_DATA EQU 071h
+
+;
+; PCI Configuration definitions
+;
+PCI_CFG EQU 1 << 01Fh ; PCI configuration access mechanism
+PCI_ADDRESS_PORT EQU 0CF8h
+PCI_DATA_PORT EQU 0CFCh
+
+;
+; LPC-ISA Bridge PCI Config Registers
+;
+LPC_PFA EQU 00A3h ; B0:D14:F3 (Legacy Block)
+ LPC_IO_PDE EQU 0044h ; IO Port Decode Enable
+ LPC_IOMEM_PDE EQU 0048h ; IO or Memory Port Decode Enable
+ LPC_BASE_WIDE_PORT EQU 0064H
+ LPC_WIDE_IO_EN EQU 0074H
+ LPC_WIDE_IO2 EQU 0090H
+ LPC_SPI_BASE_ADDR EQU 00A0H ; SPI BAR = {SPI_BaseAddr[31:8],8'b0}
+ ; HFP BAR = {SPI_BaseAddr[31:8],8'b0} +
0x0000_1000
+ ; eSPI BAR = {SPI_BaseAddr[31:8],8'b0} +
0x0001_0000
+
+ESPI_SLAVE0_DECODE_EN EQU 0040h
+ ESPI_SLAVE0_DECODE_EN_IO_80_EN EQU 04h ; Port 80 decode enabled
+
+APIC_BASE_ADDRESS EQU 0000001Bh
+APIC_BSC EQU 8 ; Boot Strap Core
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.c
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.c
new file mode 100644
index 0000000000..c5f7cc6018
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.c
@@ -0,0 +1,196 @@
+/** @file
+Platform SEC Library for Quark.
+
+Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+Copyright (c) 2013-2015 Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/TemporaryRamSupport.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/MtrrLib.h>
+
+/**
+
+ Entry point to the C language phase of SEC. After the SEC assembly
+ code has initialized some temporary memory and set up the stack,
+ the control is transferred to this function.
+
+ @param SizeOfRam Size of the temporary memory available for use.
+ @param TempRamBase Base address of temporary ram
+ @param BootFirmwareVolume Base address of the Boot Firmware Volume.
+
+**/
+VOID
+EFIAPI
+SecStartup (
+ IN UINT32 SizeOfRam,
+ IN UINT32 TempRamBase,
+ IN VOID *BootFirmwareVolume
+ );
+
+/**
+ Auto-generated function that calls the library constructors for all of the
module's
+ dependent libraries. This function must be called by the SEC Core once a
stack has
+ been established.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ VOID
+ );
+
+/**
+
+ Entry point to the C language phase of PlatformSecLib. After the SEC
assembly
+ code has initialized some temporary memory and set up the stack, control is
+ transferred to this function.
+
+**/
+VOID
+EFIAPI
+PlatformSecLibStartup (
+ VOID
+ )
+{
+ //
+ // Process all library constructor functions linked to SecCore.
+ // This function must be called before any library functions are called
+ //
+ ProcessLibraryConstructorList ();
+
+ //
+ // Set write back cache attribute for SPI FLASH
+ //
+
+ //
+ // Set write back cache attribute for 512KB Embedded SRAM
+ //
+
+ //
+ // Pass control to SecCore module passing in the size of the temporary RAM in
+ // Embedded SRAM, the base address of the temporary RAM in Embedded SRAM, and
+ // the base address of the boot firmware volume. The top 32KB of the 512 KB
+ // embedded SRAM are used as temporary RAM.
+ //
+ SecStartup (
+ SIZE_128KB,
+ BASE_64KB + BASE_128KB,
+ (VOID *)(UINTN)(PcdGet32 (PcdMemoryFvRecoveryBase))
+ );
+}
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData and PPI list that is
+ passed to PEI Core.
+
+ @param SecCoreData The same parameter as passing to PEI core. It
+ could be overridden by this function.
+ @param PpiList The default PPI list passed from generic SEC
+ part.
+
+ @return The final PPI list that platform wishes to passed to PEI core.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ )
+{
+ MtrrSetMemoryAttribute (PcdGet32 (PcdMemoryFvRecoveryBase), PcdGet32
(PcdMemoryFvMainSize) + PcdGet32 (PcdFlashFvRecoverySize), CacheWriteBack);
+ return NULL;
+}
+
+/**
+ This interface conveys state information out of the Security (SEC) phase
into PEI.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param StructureSize Pointer to the variable describing size of
the input buffer.
+ @param PlatformInformationRecord Pointer to the
EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ )
+{
+ UINT32 *BIST;
+ UINT32 Size;
+ UINT32 Count;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ UINT32 *TopOfStack;
+
+ //
+ // Top of the stack is the top of the 512KB Embedded SRAM region
+ //
+ TopOfStack = (UINT32 *)(FixedPcdGet32
(PcdPeiCorePeiPreMemoryStackBaseAddress) +
+ FixedPcdGet32 (PcdPeiCorePeiPreMemoryStackSize));
+
+ GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
+ if (GuidHob != NULL) {
+ Size = GET_GUID_HOB_DATA_SIZE (GuidHob);
+ BIST = GET_GUID_HOB_DATA (GuidHob);
+ } else {
+ //
+ // The entries of BIST information, together with the number of them,
+ // reside in the bottom of stack, left untouched by normal stack operation.
+ // This routine copies the BIST information to the buffer pointed by
+ // PlatformInformationRecord for output.
+ //
+ Count = *(TopOfStack - 1);
+ Size = Count * sizeof (IA32_HANDOFF_STATUS);
+ BIST = (UINT32 *)((UINT32)TopOfStack - sizeof (UINT32) - Size);
+
+ //
+ // Copy Data from Stack to Hob to avoid data is lost after memory is ready.
+ //
+ BuildGuidDataHob (
+ &gEfiSecPlatformInformationPpiGuid,
+ BIST,
+ (UINTN)Size
+ );
+ GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
+ Size = GET_GUID_HOB_DATA_SIZE (GuidHob);
+ BIST = GET_GUID_HOB_DATA (GuidHob);
+ }
+
+ if ((*StructureSize) < (UINT64)Size) {
+ *StructureSize = Size;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ *StructureSize = Size;
+ CopyMem (PlatformInformationRecord, BIST, Size);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This interface disables temporary memory in SEC Phase.
+**/
+VOID
+EFIAPI
+SecPlatformDisableTemporaryMemory (
+ VOID
+ )
+{
+}
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf
new file mode 100644
index 0000000000..baa7939e46
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf
@@ -0,0 +1,61 @@
+#/** @file
+# Platform SEC Library for Quark.
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+# Copyright (c) 2013-2015 Intel Corporation.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformSecLib
+ FILE_GUID = E9536686-F280-4908-88DA-DBBCD0186A6A
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecLib
+ MODULE_UNI_FILE = PlatformSecLibModStrs.uni
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformSecLib.c
+
+[Sources.IA32]
+ Ia32/Flat32.nasm
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ VanGoghCommonPkg/AmdCommonPkg.dec
+ ChachaniBoardPkg/Project.dec
+
+[LibraryClasses]
+ DebugLib
+ BaseLib
+ BaseMemoryLib
+ PciLib
+ PcdLib
+ HobLib
+ MtrrLib
+
+[Pcd]
+ gPlatformPkgTokenSpaceGuid.PcdFlashFvRecoverySize ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gPlatformPkgTokenSpaceGuid.PcdMemoryFvRecoveryBase
+ gAmdCommonPkgTokenSpaceGuid.PcdMemoryFvMainSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+ gPlatformPkgTokenSpaceGuid.PcdPeiCorePeiPreMemoryStackBaseAddress
+ gPlatformPkgTokenSpaceGuid.PcdPeiCorePeiPreMemoryStackSize
+ gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA ## CONSUMES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD ## CONSUMES
+
+[Ppis]
+ gEfiSecPlatformInformationPpiGuid ## UNDEFINED # it is used as GUIDED HOB
diff --git
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni
new file mode 100644
index 0000000000..93ee4a65dc
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni
@@ -0,0 +1,19 @@
+// /** @file
+// PlatformSecLib Localized Abstract and Description Content
+//
+// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+// Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT
+#language en-US
+"SEC Platform Library "
+
+#string STR_MODULE_DESCRIPTION
+#language en-US
+"Provides a platform-specific function to be used during the SEC stage of
POST. "
+
+
--
2.31.1
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