The ResetVector decides at runtime (depending in CPU capabilities)
whenever it uses 5-level paging or not. Firmware builds with 5-level
paging enabled (PcdUse5LevelPageTable=TRUE) may run run in 4-level
paging mode. The code handles that just fine, by looking at the la57
bit in cr4 instead of checking PcdUse5LevelPageTable.
The ASSERT is not correct, remove it.
Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
---
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 980c2002d4f5..575e396eeffd 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -745,7 +745,6 @@ CreateIdentityMappingPageTables (
//
Cr4.UintN = AsmReadCr4 ();
Page5LevelSupport = (Cr4.Bits.LA57 != 0);
- ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport);
} else {
//
// If cpu runs in 32bit protected mode PEI, Page table Level in DXE is
decided by PCD and feature capability.
--
2.43.0
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