On 20/01/2024 07:03, Ni, Ray wrote:
Can you submit another patch to add Iret.h to the INF file [Sources] section?
Without that, incremental build might not work if changes are made in Iret.h.
Good catch, thank you. I will send a v2.
It doesn't support non-x86 CPU. Will ARM have similar problems?
+Ard,
The underlying issue is not x86-specific, so it would make sense for all
timer interrupt handlers to make use of NestedInterruptTplLib.
The Arm ARM states in D1.3.2 that when an interrupt is raised, the
PSTATE.I and PSTATE.F bits are both set to 1. I believe the following
code in Iret.c should therefore work for AArch64:
+ #elif defined (MDE_CPU_AARCH64)
+
+ //
+ // Set IRQ-disabled and FIQ-disabled flags.
+ //
+ SystemContext.SystemContextAArch64->SPSR |= (SPSR_I | SPSR_F);
+
(plus whatever .inf changes are needed to pick up the ArmLib headers
where SPSR_I and SPSR_F are defined).
Thanks,
Michael
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