Oh, thanks for your comments! Will correct it in next version patch.
Thanks,
Dun
-----Original Message-----
From: Laszlo Ersek <ler...@redhat.com>
Sent: Thursday, January 11, 2024 4:48 PM
To: Tan, Dun <dun....@intel.com>; devel@edk2.groups.io
Cc: Ni, Ray <ray...@intel.com>; Kumar, Rahul R <rahul.r.ku...@intel.com>; Gerd
Hoffmann <kra...@redhat.com>
Subject: Re: [Patch V2] UefiCpuPkg:Limit PhysicalAddressBits in speicial case
On 1/11/24 03:11, Dun Tan wrote:
> When creating smm page table, limit maximum supported physical address
> bits returned by
> CalculateMaximumSupportAddress() to 47 if 5-Level Paging is disabled.
> When 5-Level Paging is disabled and the PhysicalAddressBits retrived
> from CPU HOB or CpuId is bigger than 47, and since virtual addresses
> are sign-extended, only [0, 2^47-1] range in 52-bit physical address
> is mapped in page table.
>
> Signed-off-by: Dun Tan <dun....@intel.com>
> Cc: Ray Ni <ray...@intel.com>
> Cc: Laszlo Ersek <ler...@redhat.com>
> Cc: Rahul Kumar <rahul1.ku...@intel.com>
> Cc: Gerd Hoffmann <kra...@redhat.com>
> ---
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
I'll let Gerd review this (thanks!), I just want to point out a typo in the
subject: "speicial" should be "special".
Thanks
Laszlo
>
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> index ddd9be66b5..35c282a771 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> @@ -137,11 +137,13 @@ GetSubEntriesNum (
> /**
> Calculate the maximum support address.
>
> + @param[in] Is5LevelPagingNeeded If 5-level paging enabling is needed.
> +
> @return the maximum support address.
> **/
> UINT8
> CalculateMaximumSupportAddress (
> - VOID
> + BOOLEAN Is5LevelPagingNeeded
> )
> {
> UINT32 RegEax;
> @@ -164,6 +166,15 @@ CalculateMaximumSupportAddress (
> }
> }
>
> + //
> + // Only [0, 2^47 -1] in 52-bit physical addresses is mapped in page
> + table // when 5-Level Paging is disabled.
> + //
> + ASSERT (PhysicalAddressBits <= 52); if (!Is5LevelPagingNeeded &&
> + (PhysicalAddressBits > 47)) {
> + PhysicalAddressBits = 47;
> + }
> +
> return PhysicalAddressBits;
> }
>
> @@ -197,7 +208,7 @@ SmmInitPageTable (
> mCpuSmmRestrictedMemoryAccess = PcdGetBool
> (PcdCpuSmmRestrictedMemoryAccess);
> m1GPageTableSupport = Is1GPageSupport ();
> m5LevelPagingNeeded = Is5LevelPagingNeeded ();
> - mPhysicalAddressBits = CalculateMaximumSupportAddress ();
> + mPhysicalAddressBits = CalculateMaximumSupportAddress
> (m5LevelPagingNeeded);
> PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1);
> if (m5LevelPagingNeeded) {
> mPagingMode = m1GPageTableSupport ? Paging5Level1GB :
> Paging5Level;
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