This series adds the support for RISC-V Sstc extension in EDK2 timer
implementation. Sstc extension allows S-mode software to program the
timer directly without using SBI calls.
Currently, PCD variable is used to detect whether feature is enabled. By
default the feature is enabled and platforms need to set the PCD to
disable the feature if Sstc is not supported.
For RiscVVirtQemu, it is disabled by default (until extension discovery
feature is enabled).
Changes since v1:
1) Updated "PATCH 3" to address Laszlo's comments.
2) Updated RB tag for PATCH 4.
Cc: Andrei Warkentin <andrei.warken...@intel.com>
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Sunil V L (4):
MdePkg.dec: RISC-V: Define override bit for Sstc extension
MdePkg/BaseLib: RISC-V: Add function to update stimecmp register
UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc
OvmfPkg/RiscVVirt: Override Sstc extension
MdePkg/MdePkg.dec | 2 +
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 +
MdePkg/Include/Library/BaseLib.h | 5 ++
.../Include/Register/RiscV64/RiscVEncoding.h | 3 ++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 49 +++++++++++++++++--
MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 7 +++
8 files changed, 67 insertions(+), 4 deletions(-)
--
2.34.1
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