Reviewed-by: Chasel Chiu <chasel.c...@intel.com>
Thanks,
Chasel
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desim...@intel.com>
> Sent: Monday, November 27, 2023 5:04 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.c...@intel.com>
> Subject: [edk2-platforms][PATCH v1] PurleyOpenBoardPkg/BoardMtOlympus: Fix
> Build
>
> Updates Microcode and Silicon FV sizes so they can accomodate the newest
> content.
>
> Cc: Chasel Chiu <chasel.c...@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
> ---
> .../BoardMtOlympus/OpenBoardPkg.fdf | 25 +++++++++++--------
> 1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git
> a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> index 413d98a070..86d1673458 100644
> --- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> @@ -1,7 +1,7 @@
> ## @file
> # FDF file for the MtOlympus board.
> #
> -# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2018 - 2023, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -43,11 +43,11 @@ FV =
> FvOsBoot
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSp
> aceGuid.PcdFlashFvFspUSize
> FV = FvLateSiliconCompressed
>
> -0x00900000|0x00400000
> +0x00900000|0x00300000
>
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgToke
> nSpaceGuid.PcdFlashFvUefiBootSize
> FV = FvUefiBoot
>
> -0x00D00000|0x0007C000
> +0x00C00000|0x0007C000
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeMo
> dulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> #NV_VARIABLE_STORE
> DATA = {
> @@ -86,10 +86,10 @@ DATA = {
> 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
>
> -0x00D7C000|0x00002000
> +0x00C7C000|0x00002000
> #NV_EVENT_LOG
>
> -0x00D7E000|0x00002000
> +0x00C7E000|0x00002000
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMde
> ModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> #NV_FTW_WORKING
> DATA = {
> @@ -103,28 +103,28 @@ DATA = {
> 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
>
> -0x00D80000|0x00080000
> +0x00C80000|0x00080000
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeM
> odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> #NV_FTW_SPARE
>
>
> -0x00E00000|0x00010000
> +0x00D00000|0x00030000
>
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTok
> enSpaceGuid.PcdFlashNvStorageMicrocodeSize
> FV = MICROCODE_FV
>
> -0x00E10000|0x00010000
> +0x00D30000|0x00010000
>
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvPostMemorySize
> FV = FvPostMemory
>
> -0x00E20000|0x00030000
> +0x00D40000|0x00020000
>
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSp
> aceGuid.PcdFlashFvFspSSize
> FILE =
> $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMe
> morySilicon.Fv
>
> -0x00E50000|0x00060000
> +0x00D60000|0x00050000
>
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvPreMemorySize
> FV = FvPreMemory
>
> -0x00EB0000|0x00130000
> +0x00DB0000|0x00230000
>
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSp
> aceGuid.PcdFlashFvFspMSize
> FILE =
> $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemo
> rySilicon.Fv
>
> @@ -135,6 +135,9 @@ FILE =
> $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempM
> emoryS
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress +
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
>
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
> +
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress +
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
>
> --
> 2.39.2.windows.1
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