On Mon, Nov 13, 2023 at 01:59:48PM +0800, xieyuanh wrote: > From: Yuanhao Xie <yuanhao....@intel.com> > > This patch synchronizes the No-Execute bit in the IA32_EFER > register for the APs before the RestoreVolatileRegisters operation. > > The commit 964a4f0, titled "Eliminate the second INIT-SIPI-SIPI > sequence," replaces the second INIT-SIPI-SIPI sequence with the BSP > calling the SwitchApContext function to initiate a specialized start-up > signal, waking up APs in the DXE instead of using INIT-SIPI-SIPI. > > Due to this change, the logic for "Enable execute disable bit" in > MpFuncs.nasm is no longer executed. However, to ensure the proper setup > of the page table, it is necessary to synchronize the IA32_EFER.NXE for > APs before executing RestoreVolatileRegisters . > > Based on SDM: > If IA32_EFER.NXE is set to 1, it signifies execute-disable, meaning > instruction fetches are not allowed from the 4-KByte page controlled by > this entry. Conversely, if it is set to 0, it is reserved. > > Signed-off-by: Yuanhao Xie <yuanhao....@intel.com> > Cc: Eric Dong <eric.d...@intel.com> > Cc: Ray Ni <ray...@intel.com> > Cc: Rahul Kumar <rahul1.ku...@intel.com> > Cc: Gerd Hoffmann <kra...@redhat.com>
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