On 01/11/2023 20:17, Joe L wrote:
Thanks for the discussion,
Are we saying that DataSynchronizationBarrier () before the return
from RootBridgeIoPciAccess() is not strong enough to determine that
the final ECAM write would have completed? According to Learn the
architecture - ARMv8-A memory systems
<https://developer.arm.com/documentation/100941/0101/Barriers> the
DSB should block "execution of any further instructions, not just
loads or stores, until synchronization is complete". To me this means
that for Arm the DSB will stall any subsequent instructions until the
completion for the ECAM write is received by the processor.
I honestly can't tell from the wording there whether or not DSB would
guarantee that the configuration space write has completed all the way
to the target PCIe device (as opposed to e.g. completing as far as the
host bridge, or to an intermediate PCIe bridge).
I don't know the answer, and it feels like the kind of messy area where
adding a barrier will definitely reduce the probability of the issue
occurring but might not guarantee a fix, which is a bad situation to be
left in.
Though if an architecture-agnostic solution is desired the readback
before returning from RootBridgeIoPciAccess() does make sense.
Personally I like having an architecture-agnostic solution, and I'll be
updating the ECAM driver in iPXE to use the readback approach.
If the access spanned multiple DWORDs then should a read from the
final aligned DWORD in the "buffer" be sufficient?
Quite possibly. Given that PCIe configuration space accesses are never
performance-critical, I'm not sure it's worth the optimisation, but I'll
defer to the people who actually have to implement it in EDK2.
Thanks,
Michael
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