Nhi says that reading LINK_CONTROL_LINK_STATUS_REG is redundant; its only
use was debugging (before commit 380b4b40c60d). Thus, we can go farther
than commit 2e27c62ef000, and remove the MmioRead32() call altogether.
Build-tested with "Jade.dsc".
Cc: Chuong Tran <chu...@os.amperecomputing.com>
Cc: Leif Lindholm <quic_llind...@quicinc.com>
Cc: Nhi Pham <n...@os.amperecomputing.com>
Cc: Rebecca Cran <rebe...@os.amperecomputing.com>
Suggested-by: Nhi Pham <n...@os.amperecomputing.com>
Signed-off-by: Laszlo Ersek <ler...@redhat.com>
---
Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
index fa00c1e36999..dea2e6406dfd 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
+++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
@@ -1744,7 +1744,6 @@ Ac01PcieCoreUpdateLink (
)
{
AC01_PCIE_CONTROLLER *Pcie;
- PHYSICAL_ADDRESS CfgBase;
UINT8 PcieIndex;
UINT32 Index;
@@ -1761,12 +1760,10 @@ Ac01PcieCoreUpdateLink (
// Loop for all controllers
for (PcieIndex = 0; PcieIndex < RootComplex->MaxPcieController; PcieIndex++)
{
Pcie = &RootComplex->Pcie[PcieIndex];
- CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum <<
DEV_SHIFT);
if (Pcie->Active && !Pcie->LinkUp) {
if (PcieLinkUpCheck (Pcie)) {
Pcie->LinkUp = TRUE;
- (VOID)MmioRead32 (CfgBase + PCIE_CAPABILITY_BASE +
LINK_CONTROL_LINK_STATUS_REG);
// Doing link checking and recovery if needed
Ac01PcieCoreQoSLinkCheckRecovery (RootComplex, PcieIndex);
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