On Thu, Oct 12, 2023 at 07:29:59PM +0100, Pedro Falcato wrote: > On Thu, Oct 12, 2023 at 1:12 PM Sunil V L <suni...@ventanamicro.com> wrote: > > > > Hi Ray, > > > > On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote: > > > Introduce a PCD to control the maximum SATP mode that MMU allowed > > > to use. This PCD helps RISC-V platform set bare or minimum SATP mode > > > during bring up to debug memory map issue. > > > > > Could you help with review of this? > > It seems glaring to me that Maintainers.txt needs some sort of > > RISCV > F: */*RiscV*/ > > pattern for riscv architectural changes across all packages - I'm not > sure how much value the x86 Intel folks can add to RISCV or ARM code > review and merging, apart from the traditional UEFI/tianocore > feedback. > I agree. For RISC-V only changes, I don't bother the PKG maintainers. But like in this case, UefiCpuPkg.dec is modified, I think it is my duty to make sure PKG maintainers are notified and sufficient time given for them to ACK. I consider "no response" after few days as "no objection" and merge the changes.
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