Reviewed-by: Sai Chaganty <rangasai.v.chaga...@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbe...@intel.com>
Sent: Wednesday, September 13, 2023 3:05 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbe...@intel.com>; Chaganty, Rangasai V
<rangasai.v.chaga...@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desim...@intel.com>; Chuang, Rosen <rosen.chu...@intel.com>
Subject: [PATCH 1/4] AlderlakeOpenBoardPkg/AlderlakePRvp: Add DSC and build
files
Adds the DSC and build files necessary to build the
AlderlakePRvp board instance.
Key files:
* build_config.cfg - Board-specific build configuration file.
* OpenBoardPkg.dsc - The AlderlakePRvp board description file.
* OpenBoardPkgPcd.dsc - Used for other PCD customization.
* OpenBoardPkg.fdf - The AlderlakePRvp board flash file.
* OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values.
* FlashMapInclude.fdf - AlderlakePRvp flash map file.
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Rosen Chuang <rosen.chu...@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbe...@intel.com>
---
.../Include/Fdf/FlashMapInclude.fdf | 52 ++
.../AlderlakePRvp/OpenBoardPkg.dsc | 481 ++++++++++++
.../AlderlakePRvp/OpenBoardPkg.fdf | 724 ++++++++++++++++++
.../AlderlakePRvp/OpenBoardPkgBuildOption.dsc | 161 ++++
.../AlderlakePRvp/OpenBoardPkgPcd.dsc | 371 +++++++++
.../AlderlakePRvp/build_config.cfg | 34 +
6 files changed, 1823 insertions(+)
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgBuildOption.dsc
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/build_config.cfg
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
new file mode 100644
index 0000000000..03c198c06a
--- /dev/null
+++
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
@@ -0,0 +1,52 @@
+## @file
+# FDF file of Platform.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#=================================================================================#
+# 16 MB BIOS - for FSP wrapper
+#=================================================================================#
+DEFINE FLASH_BASE =
0xFF000000 #
+DEFINE FLASH_SIZE =
0x01000000 #
+DEFINE FLASH_BLOCK_SIZE =
0x00010000 #
+DEFINE FLASH_NUM_BLOCKS =
0x00000100 #
+#=================================================================================#
+
+#=================================================================================#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =
0x00000000 # Flash addr (0xFF000000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =
0x00060000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =
0x00000000 # Flash addr (0xFF000000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =
0x0002E000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =
0x0002E000 # Flash addr (0xFF02E000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =
0x00002000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =
0x00030000 # Flash addr (0xFF030000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =
0x00030000 #
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =
0x000E0000 # Flash addr (0xFF0E0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =
0x00310000 #
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset =
0x003F0000 # Flash addr (0xFF400000)
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize =
0x00360000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =
0x00750000 # Flash addr (0xFF760000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =
0x00090000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =
0x007E0000 # Flash addr (0xFF7F0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =
0x000A0000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =
0x00880000 # Flash addr (0xFF860000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =
0x00180000 #
+
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset =
0x00A00000 # Flash addr (0xFFA00000)
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize =
0x00080000 # Keep 0x80000 or larger
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =
0x00A80000 # Flash addr (0xFFA80000)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
0x00230000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =
0x00CB0000 # Flash addr (0xFFCB0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =
0x00040000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =
0x00CF0000 # Flash addr (0xFFCF0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =
0x000A0000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =
0x00D90000 # Flash addr (0xFFD90000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =
0x00150000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =
0x00EE0000 # Flash addr (0xFFEE0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =
0x00010000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =
0x00EF0000 # Flash addr (0xFFEF0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =
0x00110000
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc
new file mode 100644
index 0000000000..4cdc9c0192
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc
@@ -0,0 +1,481 @@
+## @file
+# The main build description file for the AlderlakePRvp board.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+[Defines]
+ #
+ # Set platform specific package/folder name, same as passed from PREBUILD
script.
+ # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package
build folder
+ # DEFINE only takes effect at R9 DSC and FDF.
+ #
+ DEFINE PLATFORM_PACKAGE = MinPlatformPkg
+ DEFINE PLATFORM_SI_PACKAGE = AlderlakeSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = AlderlakeSiliconBinPkg
+ DEFINE PLATFORM_FSP_BIN_PACKAGE =
AlderLakeFspBinPkg/Client/AlderLakeP
+ DEFINE PLATFORM_BOARD_PACKAGE = AlderlakeOpenBoardPkg
+ DEFINE BOARD = AlderlakePRvp
+ DEFINE PROJECT =
$(PLATFORM_BOARD_PACKAGE)/$(BOARD)
+ #
+ # Default value for OpenBoardPkg.fdf use
+ #
+ DEFINE BIOS_SIZE_OPTION = SIZE_160
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = $(PLATFORM_BOARD_PACKAGE)
+ PLATFORM_GUID = EB89E595-7D9D-4422-A277-A50B5AFD3E16
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(PROJECT)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = ALL
+
+
+ FLASH_DEFINITION = $(PROJECT)/OpenBoardPkg.fdf
+
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+ FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
+ DEFINE TOP_MEMORY_ADDRESS = 0x0
+
+ #
+ # Include PCD configuration for this board
+ #
+ !include OpenBoardPkgPcd.dsc
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+################################################################################
+[SkuIds] # SkuId = PcdBoardBomId <<
16 | PcdBoardRev << 8 | PcdBoardId
+ 0|DEFAULT # The entry: 0|DEFAULT is
reserved and always required.
+ 0x000012|SkuIdAdlPDdr5Rvp
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses.common]
+ PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
+
ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
+
+
PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf
+
PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+
PlatformHookLib|$(PLATFORM_BOARD_PACKAGE)/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+
+
SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+
SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+
+#
+# Platform
+#
+
+ FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
+
FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+
FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
+
FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+
+
ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
+
+
BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+
+
PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
+
PostCodeMapLib|PostCodeDebugFeaturePkg/Library/PostCodeMapLib/PostCodeMapLib.inf
+
+
PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+
FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
+
FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+
+#
+# Platform
+#
+
PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+
BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf
+ BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/Product/Alderlake/SiPkgCommonLib.dsc
+
+#
+# Features
+#
+
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+[LibraryClasses.common.PEIM]
+
FirmwareBootMediaInfoLib|BoardModulePkg/Library/PeiFirmwareBootMediaInfoLib/PeiFirmwareBootMediaInfoLib.inf
+
+[LibraryClasses.IA32]
+#
+# PEI phase common
+#
+
+ ResetSystemLib|MdeModulePkg/Library/PeiResetSystemLib/PeiResetSystemLib.inf
+
+
+!if $(TARGET) == DEBUG
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+!endif
+
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+
MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+
BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+
+
BoardConfigLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/Product/Alderlake/SiPkgPeiLib.dsc
+
+#
+# Features
+#
+
FirmwareBootMediaLib|IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/PeiFirmwareBootMediaLib.inf
+
Usb3DebugPortLib|Usb3DebugFeaturePkg/Library/Usb3DebugPortLib/Usb3DebugPortLibNull.inf
+
+#
+# SmmAccess
+#
+
SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf
+
+
PeiGetFvInfoLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
+
PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
+
+[LibraryClasses.IA32.SEC]
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+
Usb3DebugPortLib|Usb3DebugFeaturePkg/Library/Usb3DebugPortLib/Usb3DebugPortLibNull.inf
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+
ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf
+
SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+
+[LibraryClasses.IA32.PEIM]
+
+
FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+
+
+ #
+ # Use Null library instance to skip MTRR initialization from MinPlatformPkg
PlatformInit modules.
+ # MTRR configuration will be done by FSP or OpenBoardPlatformInit modules.
+ #
+
SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
+
+ #
+ # This is library instance of Cpu Hob Library, replacing the library
instance from MinPlatform.
+ #
+
ReportCpuHobLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
+
+!if $(TARGET) == DEBUG
+ #
+ # This is for reducing NATIVE DEBUG binary size, replacing some library
routines with PPI.
+ #
+ DebugLib|MdeModulePkg/Library/PeiDebugLibDebugPpi/PeiDebugLibDebugPpi.inf
+!endif
+
+
+[LibraryClasses.X64]
+ #
+ # DXE phase common
+ #
+
+
FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformLib/DxeFspWrapperPlatformLib.inf
+
+
+!if $(TARGET) == DEBUG
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+!endif
+
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf
+
MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+
BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+
MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
+
BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
+
SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
+
TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+ TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/Product/Alderlake/SiPkgDxeLib.dsc
+
+
FirmwareBootMediaLib|IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/DxeSmmFirmwareBootMediaLib.inf
+
Usb3DebugPortLib|Usb3DebugFeaturePkg/Library/Usb3DebugPortLib/Usb3DebugPortLibNull.inf
+
+
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+ TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+
+!if $(TARGET) == DEBUG
+
SpiFlashCommonLib|$(PLATFORM_BOARD_PACKAGE)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+!endif
+
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf
+
MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+
BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+
+
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+
ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+
+
+ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
+
+[Components.IA32]
+
+#
+# Common
+#
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
+
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ !if $(TARGET) == DEBUG
+
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+ !endif
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ MdeModulePkg/Universal/SectionExtractionPei/SectionExtractionPei.inf {
+ <LibraryClasses>
+
NULL|SecurityPkg/Library/PeiRsa2048Sha256GuidedSectionExtractLib/PeiRsa2048Sha256GuidedSectionExtractLib.inf
+ }
+
+ #
+ # FSP wrapper SEC Core
+ #
+ UefiCpuPkg/SecCore/SecCore.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+
+
+#
+# CpuFeatures PEIM
+#
+ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf {
+ <LibraryClasses>
+
RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
+ NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
+ }
+#
+# This is for reducing NATIVE DEBUG binary size, replacing some library
routines with PPI.
+#
+!if $(TARGET) == DEBUG
+ MdeModulePkg/Universal/DebugServicePei/DebugServicePei.inf {
+ <LibraryClasses>
+
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+ }
+!endif
+
+#
+# Platform
+#
+ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ NULL|$(PROJECT)/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
+ }
+
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+ NULL|$(PROJECT)/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
+ }
+
$(PLATFORM_BOARD_PACKAGE)/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
+
+ BoardModulePkg/FirmwareBootMediaInfo/FirmwareBootMediaInfoPei.inf
+
+ $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
+ $(PLATFORM_PACKAGE)/Services/StallServicePei/StallServicePei.inf
+
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
{
+ <LibraryClasses>
+
SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiPreMemSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf
+
SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+ }
+
+
$(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf {
+ <LibraryClasses>
+
SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiPostMemSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf
+
SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+ }
+
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {
+ <LibraryClasses>
+ #
+ # In FSP Dispatch mode below dummy library should be linked to
bootloader PEIM
+ # to build all DynamicEx PCDs that FSP consumes into bootloader PCD
database.
+ #
+
NULL|$(PLATFORM_FSP_BIN_PACKAGE)/Library/FspPcdListLib/FspPcdListLibNull.inf
+ }
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf {
+ <LibraryClasses>
+ }
+
+#
+# Security
+#
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+#
+# Features
+#
+
+ MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf {
+ <LibraryClasses>
+
ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
+ }
+
+[Components.X64]
+
+#
+# Common
+#
+
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
+
+
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
{
+ <LibraryClasses>
+ # Use BaseDebugLibNull for save the binary size.
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ }
+
+ MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf {
+ <LibraryClasses>
+ # Use BaseDebugLibNull for save the binary size.
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+
+ }
+
+ #
+ # Generic EDKII Driver
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ !if gPlatformModuleTokenSpaceGuid.PcdLzmaEnable == TRUE
+
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ !endif
+ }
+
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+#
+#UEFI Shell
+#
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
+
+#
+# Silicon
+#
+!include $(PLATFORM_SI_PACKAGE)/Product/Alderlake/SiPkgDxe.dsc
+$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
+
+#
+# SMBIOS
+#
+!if gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+!endif
+
+
+#
+# SmmAccess
+#
+ IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf
+
+#
+# Platform
+#
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+ $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
+ $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+!endif #PcdBootToShellOnly
+
+#
+# OS Boot
+#
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+ $(PLATFORM_BOARD_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf
+ $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
+ }
+
+!if gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE
+ IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+!endif # gSiPkgTokenSpaceGuid.PcdSmmVariableEnable
+
+!endif #PcdBootToShellOnly
+
+#
+# Security
+#
+ $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+
+#
+# Build Options
+#
+!include $(PLATFORM_SI_PACKAGE)/Product/Alderlake/SiPkgBuildOption.dsc
+!include OpenBoardPkgBuildOption.dsc
+
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf
new file mode 100644
index 0000000000..f1ce271b1d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf
@@ -0,0 +1,724 @@
+## @file
+# FDF file of Platform.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
+
+#
+# FV compression algorithm
+#
+!if gPlatformModuleTokenSpaceGuid.PcdLzmaEnable == TRUE
+ DEFINE FVCOMPRESSIONGUID = gLzmaCustomDecompressGuid
+ DEFINE MODULECOMPRESS = LzmaCompress
+!else
+ DEFINE FVCOMPRESSIONGUID = gTianoCustomDecompressGuid # TianoCompress
+ DEFINE MODULECOMPRESS = LzmaCompress
+!endif
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.AlderlakePRvp]
+#
+# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks,
cannot be
+# assigned with PCD values. Instead, it uses the definitions for its variety,
which
+# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
+#
+BaseAddress = $(FLASH_BASE) |
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the
FLASH Device.
+Size = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
#The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = $(FLASH_BLOCK_SIZE)
+NumBlocks = $(FLASH_NUM_BLOCKS)
+
+DEFINE SIPKG_DXE_SMM_BIN = INF
+DEFINE SIPKG_PEI_BIN = INF
+
+# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro
expression is not supported.
+# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get
the real CodeCache base address.
+SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) +
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) -
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of
different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required)
followed by
+# the pipe "|" character, followed by the size of the region, also in hex with
the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+# Fv Size can be adjusted
+#
+################################################################################
+
+#
+# Firmware Volumes for 16MB Region at reset vector
+#
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x60000
+ 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ #
+ # Be careful on CheckSum field.
+ #
+ 0x48, 0x00, 0x2E, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 6 Blocks 0x10000 Bytes / Block
+ 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6,
0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ #Size: 0x2E000
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of
EFI_FIRMWARE_VOLUME_HEADER) = 0x2DFB8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xDF, 0x02, 0x00,
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b,
0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
+
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+FV = FvAdvanced
+
+gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize
+gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize
+FV = FvOptional
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+FV = FvSecurityPreMemory
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+FV = FvOsBoot
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+FV = FvUefiBoot
+
+gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize
+gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize
+FV = FvFwBinaries
+
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+#Microcode
+FV = FvMicrocode
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+FV = FvPostMemory
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+# FSP_S Section
+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+# FSP_M Section
+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+# FSP_T Section
+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+FV = FvPreMemory
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within
a flash
+# device file. This section also defines order the components and modules are
positioned
+# within the image. The [FV] section consists of define statements, set
statements and
+# module statements.
+#
+################################################################################
+[FV.FvMicrocode]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+INF RuleOverride = MICROCODE
$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
+
+[FV.FvPreMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
+
+APRIORI PEI {
+ # Load Pcd at first, since all the other drivers depend on it.
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ # In order to support use PeiDxeDebugLibReportStatusCode as DebugLib,
+ # load ReportStatusCodeRouterPei, StatusCodeHandlerPei and
PlatformStatusCodeHandlerPei early.
+ INF
MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+ # The DebugServicePei also use PeiDxeDebugLibReportStatusCode as backend
DebugLib.
+!if $(TARGET) == DEBUG
+ INF MdeModulePkg/Universal/DebugServicePei/DebugServicePei.inf
+!endif
+}
+
+INF UefiCpuPkg/SecCore/SecCore.inf
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
+
+INF BoardModulePkg/FirmwareBootMediaInfo/FirmwareBootMediaInfoPei.inf
+
+#
+# Features
+#
+
+INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
+
+INF $(PLATFORM_PACKAGE)/Services/StallServicePei/StallServicePei.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF
$(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+!if $(TARGET) == DEBUG
+ #
+ # This is for reducing NATIVE DEBUG binary size, replacing some library
routines with PPI.
+ #
+ INF MdeModulePkg/Universal/DebugServicePei/DebugServicePei.inf
+!endif
+
+ INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+
+FILE FREEFORM = 338FA35A-CA4A-4DBC-A6F4-9BD1593B61BC {
+ SECTION RAW =
$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
+}
+
+INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf
+
+FILE FV_IMAGE = 3950B5FD-9386-40CC-8F33-C87925E663C9 {
+ SECTION FV_IMAGE = FvSecurityPreMemory
+}
+
+[FV.FvPostMemoryUncompact]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
+
+!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
+FILE FREEFORM =
PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid) {
+ SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
+ SECTION UI = "IntelGopVbt"
+}
+
+
+FILE FREEFORM = gTianoLogoGuid {
+ SECTION RAW = MdeModulePkg/Logo/Logo.bmp
+}
+!endif # PcdPeiDisplayEnable
+
+
+# Init Board Config PCD
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+INF
$(PLATFORM_BOARD_PACKAGE)/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
+INF
$(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
+INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+
+
+[FV.FvPostMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
+
+FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
+ SECTION GUIDED $(FVCOMPRESSIONGUID) PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvPostMemoryUncompact
+ }
+ SECTION GUIDED $(FVCOMPRESSIONGUID) PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityPostMemory
+ }
+ SECTION GUIDED $(FVCOMPRESSIONGUID) PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityLate
+ }
+}
+
+[FV.FvUefiBootUncompact]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
+
+APRIORI DXE {
+ # Load Pcd at first, since all the other drivers depend on it.
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ # In order to support use PeiDxeDebugLibReportStatusCode as DebugLib,
+ # load ReportStatusCodeRouterRuntimeDxe, StatusCodeHandlerRuntimeDxe and
PlatformStatusCodeHandlerRuntimeDxe early.
+ INF
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+}
+
+#
+# Board specific instance of CoreUefiBootInclude.fdf from MinPlatformPkg
+#
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
+
+
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+
+INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
+INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+#
+# UEFI Shell
+#
+# Note : gUefiShellFileGuid (7C04A583-9E3E-4f1c-AD65-E05268D0B4D1) is FILE
GUID for ShellPkg/Application/Shell/Shell.inf
+#
+FILE APPLICATION = 7C04A583-9E3E-4F1C-AD65-E05268D0B4D1 {
+ SECTION PE32 =
$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/ShellPkg/Application/Shell/Shell/OUTPUT/Shell.efi
+ SECTION UI = "EdkShell"
+}
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
+
+[FV.FvUefiBoot]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
+
+FILE FV_IMAGE = gFvUefiBootFileGuid {
+ SECTION GUIDED $(FVCOMPRESSIONGUID) PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompact
+ }
+}
+
+[FV.FvOsBootUncompact]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
+
+APRIORI DXE {
+ # In order to support use PeiDxeDebugLibReportStatusCode as DebugLib,
+ # load ReportStatusCodeRouterSmm, StatusCodeHandlerSmm and
PlatformStatusCodeHandlerSmm early.
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ INF
MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+!endif
+ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+}
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit == FALSE
+!if gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit == FALSE
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+INF RuleOverride = DRIVER_ACPITABLE
$(PLATFORM_BOARD_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
+!if gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE
+INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+!endif
+
+!endif #PcdBootToShellOnly
+!endif #PcdStopAfterMemInit
+!endif #PcdStopAfterDebugInit
+!if gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+!endif
+
+
+[FV.FvLateSilicon]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit == FALSE
+!if gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit == FALSE
+
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+$(SIPKG_DXE_SMM_BIN)
$(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
+$(SIPKG_DXE_SMM_BIN)
$(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf
+$(SIPKG_DXE_SMM_BIN)
$(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+
+!endif #PcdBootToShellOnly
+
+!endif #PcdStopAfterMemInit
+!endif #PcdStopAfterDebugInit
+
+[FV.FvOsBoot]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
+
+FILE FV_IMAGE = gFvOsBootFileGuid {
+ SECTION GUIDED $(FVCOMPRESSIONGUID) PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOsBootUncompact
+ }
+ SECTION GUIDED $(FVCOMPRESSIONGUID) PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvLateSilicon
+ }
+}
+
+[FV.FvSecurityPreMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16 #FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+[FV.FvSecurityPostMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16 #FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+[FV.FvSecurityLate]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+!endif
+
+INF IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf
+
+
+[FV.FvAdvanced]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
+
+
+[FV.FvFwBinaries]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 8B98AB22-E354-42f0-88B9-049810F0FDAA
+
+
+
+
+
+[FV.FvOptional]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 9574B1CE-EE93-451E-B500-3E5F564244DE
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the
default
+# rules for the different module type. User can add the customized rules to
define the
+# content of the FFS file.
+#
+################################################################################
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
+
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgBuildOption.dsc
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgBuildOption.dsc
new file mode 100644
index 0000000000..47002a61ca
--- /dev/null
+++
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgBuildOption.dsc
@@ -0,0 +1,161 @@
+## @file
+# platform build option configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[BuildOptions]
+
+# Define Build Options both for EDK and EDKII drivers.
+
+
+ DEFINE DSC_S3_BUILD_OPTIONS =
+
+!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
+ DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1
+!else
+ DEFINE DSC_ACPI_BUILD_OPTIONS =
+!endif
+
+
+ DEFINE BIOS_GUARD_BUILD_OPTIONS =
+
+ DEFINE OVERCLOCKING_BUILD_OPTION =
+
+ DEFINE FSP_BINARY_BUILD_OPTIONS =
+
+ DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =
+
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =
+
+ DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =
+
+
+ DEFINE TPM_BUILD_OPTION =
+
+ DEFINE TPM2_BUILD_OPTION =
+
+ DEFINE DSC_TBT_BUILD_OPTIONS =
+
+ DEFINE DSC_DCTT_BUILD_OPTIONS =
+
+ DEFINE EMB_BUILD_OPTIONS =
+
+ DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1
+
+ DEFINE DSC_KBCEMUL_BUILD_OPTIONS =
+
+ DEFINE BOOT_GUARD_BUILD_OPTIONS =
+
+ DEFINE SECURE_BOOT_BUILD_OPTIONS =
+
+ DEFINE USBTYPEC_BUILD_OPTION =
+
+ DEFINE CAPSULE_BUILD_OPTIONS =
+ DEFINE DEFAULT_BOOT_TIME_OUT_MACRO = -DDEFAULT_BOOT_TIME_OUT=5
+
+ DEFINE PERFORMANCE_BUILD_OPTION =
+
+ DEFINE DEBUGUSEUSB_BUILD_OPTION =
+
+ DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =
+
+ DEFINE DSC_SYMBOL_IN_RELEASE_BUILD_OPTIONS =
+ DEFINE DSC_SYMBOL_IN_RELEASE_LINK_BUILD_OPTIONS =
+
+ DEFINE SINITBIN_BUILD_OPTION =
+
+ DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1
+
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
$(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION)
$(DEFAULT_BOOT_TIME_OUT_MACRO) $(EMB_BUILD_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS)
$(DSC_TBT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS)
$(DEBUGUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(FSP_BINARY_BUILD_OPTIONS) $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS)
$(SECURE_BOOT_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS)
$(USBTYPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
+
+[BuildOptions.Common.EDKII]
+#
+# For IA32 Global Build Flag
+#
+ *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+ *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+ *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
PI_SPECIFICATION_VERSION=0x00010015
+ *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For X64 Specific Build Flag
+#
+GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
$(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+##################
+# Rsa2048Sha256Sign tool definitions
+#
+# Notes: This tool defintion uses a test signing key for development purposes
only.
+# The tool Rsa2048Sha256GenerateKeys can be used to generate a new
private/public key
+# and the gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer
PCD value.
+# A custom tool/script can be implemented using the new private/public
key with
+# the Rsa2048Sha256Sign tool and this tool defintiion can be updated to
use a
+# custom tool/script.
+#
+# Generate new private/public key and
gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer PCD value
+#
+# Rsa2048Sha256GenerateKeys.py -o MyKey.pem --public-key-hash-c MyKey.pcd
+#
+# Custom script example (MyRsa2048Sha256Sign.cmd):
+#
+# Rsa2048Sha256Sign --private-key MyKey.pem %1 %2 %3 %4 %5 %6 %7 %8 %9
+#
+# WARNING: Vendors that uses private keys are responsible for proper
management and protection
+# of private keys. Vendors may choose to use infrastructure such
as signing servers
+# or signing portals to support the management and protection of
private keys.
+#
+##################
+*_*_*_RSA2048SHA256SIGN_PATH = Rsa2048Sha256SignPlatform
+*_*_*_RSA2048SHA256SIGN_GUID = A7717414-C616-4977-9420-844712A735BF
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support page level
protection
+[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC:*_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support
MemoryAttribute table
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC:*_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support NX
protection
+[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE,
BuildOptions.common.EDKII.UEFI_DRIVER,
BuildOptions.common.EDKII.UEFI_APPLICATION]
+ #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ #GCC:*_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc
new file mode 100644
index 0000000000..3eb9a5758b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc
@@ -0,0 +1,371 @@
+## @file
+# Board description file initializes configuration (PCD) settings for the
project.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all PCD Entries used by this board.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Key Boot Stage and FSP configuration
+ ######################################
+ #
+ # Please select the Boot Stage here.
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
+
+ #
+ # 0: FSP Wrapper is running in Dispatch mode.
+ # 1: FSP Wrapper is running in API mode.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
+
+ #
+ # FALSE: The board is not a FSP wrapper (FSP binary not used)
+ # TRUE: The board is a FSP wrapper (FSP binary is used)
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00100000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+ gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
+
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport|TRUE
+ gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdAcpiEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdFspWrapperEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
+
+ #
+ # PCD declared for Fru
+ #
+ gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported|TRUE
+ gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
+
+#
+# 16 MB BIOS Flash Base Address and Size
+#
+ gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF000000
+ gSiPkgTokenSpaceGuid.PcdBiosSize|0x01000000
+ gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
+
+ #
+ # When sharing stack with boot loader, FSP only needs a small temp ram for
heap
+ #
+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000
+!else
+ #
+ # FSP Dispatch mode will not establish separate Stack or Heap.
+ #
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0
+!endif
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xC0000000
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
+
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId|0x13
+
+ gPlatformModuleTokenSpaceGuid.PcdLzmaEnable|TRUE
+ #
+ # BIOS build switches configuration
+ #
+
gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|(gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
- 0x10000000) # 0xB0000000
+
gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|(gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
- 0x11000000) # 0xAF000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x80000
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
+
+ ## Specifies the size of the microcode Region.
+ # @Prompt Microcode Region size.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
+
+#
+# NvStorage Base Address and Size
+#
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00060000
+
+ #
+ # Set the location of the DUTY_CYCLE field in the P_CNT register
+ # and indicate the width of the clock duty cycle to OS power management
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
+[PcdsFeatureFlag.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+
gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ #
+ # MinPlatform common include for required feature PCD
+ # These PCD must be set before the core include files, CoreCommonLib,
+ # CorePeiLib, and CoreDxeLib.
+ # Optional MinPlatformPkg features should be enabled after this
+ #
+ !include MinPlatformPkg/Include/Dsc/MinPlatformFeaturesPcd.dsc.inc
+
+ #
+ # Commonly used MinPlatform feature configuration logic that maps
functionity to stage
+ #
+ !include BoardModulePkg/Include/Dsc/CommonStageConfig.dsc.inc
+
+ ######################################
+ # Board Configuration
+ ######################################
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+
+
+!if $(TARGET) == DEBUG
+ !if gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable == TRUE
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
+ gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|TRUE
+ !endif
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+
gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiResetRegisterAccessSize|0x1
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aEvtBlkAccessSize|0x2
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1bEvtBlkAccessSize|0x2
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aCntBlkAccessSize|0x2
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1bCntBlkAccessSize|0x2
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x0
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm2CntBlkAccessSize|0x1
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize|0x2
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize|0x1
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe1BlkAccessSize|0x1
+
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|0
+
+
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase|0x80400000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xBFFFFFFF
+ #
+ # The PCDs are used to control the Windows SMM Security Mitigations Table -
Protection Flags
+ #
+ # BIT0: If set, expresses that for all synchronous SMM entries,SMM will
validate that input and output buffers lie entirely within the expected fixed
memory regions.
+ # BIT1: If set, expresses that for all synchronous SMM entries, SMM will
validate that input and output pointers embedded within the fixed communication
buffer only refer to address ranges \
+ # that lie entirely within the expected fixed memory regions.
+ # BIT2: Firmware setting this bit is an indication that it will not allow
reconfiguration of system resources via non-architectural mechanisms.
+ # BIT3-31: Reserved
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0xCC
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA2
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x3100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x2A
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xC4
+
+!if gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport|FALSE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07,
0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07,
0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F,
0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F,
0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00}
+!endif
+
+[PcdsFixedAtBuild.IA32]
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
+ gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
+
+[PcdsFixedAtBuild.X64]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+
+ # Default platform supported RFC 4646 languages: (American) English
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
+
+[PcdsPatchableInModule.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0304
+
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+
+
+
+[PcdsDynamicDefault]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020204C4349
+
+
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase|0xFFFFFFFFFFFFFFFF
+
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit|0x0000000000000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount|0x1
+
+
+ gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020204C4349
+
+gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFD20000
+gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000
+gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000
+
+!if $(TARGET) == DEBUG
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!endif
+
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+[PcdsDynamicHii.X64.DEFAULT]
+
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
# Variable: L"Timeout"
+
gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1
# Variable: L"HwErrRecSupport"
+
+[PcdsDynamicExDefault]
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ #
+ # Some of the PCD consumed by both FSP and bootloader should be defined
+ # here for bootloader to consume.
+ #
+
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|{0x0}
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem.GpioConfig[60].GpioPad|0x0
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|{0x0}
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable.GpioConfig[130].GpioPad|0x0
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem|{0x0}
+
gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem.GpioConfig[40].GpioPad|0x0
+ gBoardModuleTokenSpaceGuid.PcdBoardAcpiData|{0x0}
+
+ #
+ # Include FSP PCD settings.
+ #
+ !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPkgPcdShare.dsc
+
+#
+# FSP Binary base address will be set in FDF basing on flash map
+#
+gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
+
+ !include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/AllStructPCD.dsc
+
+[PcdsDynamicExVpd.common.DEFAULT]
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem| * |{CODE({
+ {0x0} // terminator
+ })}
+
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable| * |{CODE({
+ {0x0} // terminator
+ })}
+
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap| * |{CODE(
+ {0x0}
+ )}
+
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData| * |{CODE(
+ {0x0}
+ )}
+
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram| * |{CODE(
+ {0x0}
+ )}
+
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram| * |{CODE(
+ {0x0}
+ )}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/build_config.cfg
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/build_config.cfg
new file mode 100644
index 0000000000..ae391bec8c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/build_config.cfg
@@ -0,0 +1,34 @@
+# @ build_config.cfg
+# This is the AlderlakePRvp board specific build settings
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN =
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = AlderlakeOpenBoardPkg
+PROJECT = AlderlakeOpenBoardPkg/AlderlakePRvp
+BOARD = AlderlakePRvp
+FLASH_MAP_FDF =
AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
+PROJECT_DSC = AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc
+BOARD_PKG_PCD_DSC = AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS =
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = AlderlakeFspBinPkg/Client/AlderlakeP
+FSP_PKG_NAME = AlderlakeSiliconPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
--
2.36.1.windows.1
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