Add Cpu/Include, Cpu/IncludePrivate and Cpu/Library
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Isaac Oram <isaac.w.o...@intel.com>
Cc: Rosen Chuang <rosen.chu...@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbe...@intel.com>
---
.../Cpu/Include/ConfigBlock/CpuConfig.h | 86 ++++++++
.../ConfigBlock/CpuConfigLibPreMemConfig.h | 195 ++++++++++++++++++
.../ConfigBlock/CpuSecurityPreMemConfig.h | 63 ++++++
.../AlderlakeSiliconPkg/Cpu/Include/CpuRegs.h | 63 ++++++
.../Cpu/Include/Library/CpuPlatformLib.h | 42 ++++
.../Cpu/Include/Register/CommonMsr.h | 60 ++++++
.../IncludePrivate/Library/CpuInfoFruLib.h | 64 ++++++
.../CpuPlatformLibrary.c | 55 +++++
.../CpuPlatformLibrary.h | 25 +++
.../PeiDxeSmmCpuPlatformLib.inf | 41 ++++
10 files changed, 694 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/CpuRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/IncludePrivate/Library/CpuInfoFruLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
new file mode 100644
index 0000000000..9815f8b185
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h
@@ -0,0 +1,86 @@
+/** @file
+ CPU Config Block.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#define CPU_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 MicrocodePatchRegionSize;
+ EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode
patch that is suitable for this processor.
+ /**
+ Enable or Disable Advanced Encryption Standard (AES) feature.
+ For some countries, this should be disabled for legal reasons.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 AesEnable : 1;
+ /**
+ Enable or Disable Trusted Execution Technology (TXT) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 TxtEnable : 1;
+ UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon
Initialization will skip MP Initialization (including BSP) if enabled. For
non-FSP, this should always be 0.
+ /**
+ Enable or Disable or Auto for PPIN Support to view Protected Processor
Inventory Number.
+ - <b>0: Disable</b>
+ - 1: Enable
+ - 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM
is set, it is disabled.
+ **/
+ UINT32 PpinSupport : 2;
+ /**
+ Enable or Disable #AC machine check on split lock.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 AcSplitLock : 1;
+ /**
+ Enable or Disable Avx.
+ - 1: Disable
+ - <b> 0: Enable</b>
+ **/
+ UINT32 AvxDisable : 1;
+ /**
+ @deprecated
+ Enable or Disable Avx3.
+ - <b> 1: Disable</b>
+ - 0: Enable
+ **/
+ UINT32 Avx3Disable : 1;
+ /**
+ Enable or Disable X2APIC Support.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 X2ApicSupport : 1;
+ UINT32 RsvdBits : 23; ///< Reserved for future use
+ /**
+ Provide the option for platform to override the MaxSpeed field of Smbios
Type 4.
+ Value 4000 means 4000MHz.
+ If this value is not zero, it dominates the field.
+ If this value is zero, CPU RC will update the field according to the max
radio.
+ <b>default is 0.</b>
+ **/
+ UINT16 SmbiosType4MaxSpeedOverride;
+ UINT8 Reserved0[2]; ///< Reserved for future use
+} CPU_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
new file mode 100644
index 0000000000..68d4effe3f
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h
@@ -0,0 +1,195 @@
+/** @file
+ CPU Security PreMemory Config Block.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+
+#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuConfigLibPreMemConfigGuid;
+
+
+#pragma pack (push,1)
+
+/**
+ CPU Config Library PreMemory Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 HyperThreading : 1; ///< Enable or Disable Hyper
Threading; 0: Disable; <b>1: Enable</b>.
+ /**
+ Sets the boot frequency starting from reset vector.
+ - 0: Maximum battery performance.
+ - 1: Maximum non-turbo performance
+ -<b>2: Turbo performance</b>.
+ @note If Turbo is selected BIOS will start in max non-turbo mode and switch
to Turbo mode.
+ **/
+ UINT32 BootFrequency : 2;
+ /**
+ Number of processor cores to enable.
+ - <b> 0: All cores</b>
+ - 1: 1 core
+ - 2: 2 cores
+ - 3: 3 cores
+ **/
+ UINT32 ActiveCoreCount : 3; ///< @deprecated due to core active
number limitaion.
+ UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated in
C10 state. True: keeps the JTAG power up during C10 and deeper power states for
debug purpose. <b>0: False<\b>; 1: True.
+ UINT32 BistOnReset : 1; ///< <b>(Test)</b> Enable or Disable
BIST on Reset; <b>0: Disable</b>; 1: Enable.
+ /**
+ Enable or Disable Virtual Machine Extensions (VMX) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 VmxEnable : 1;
+ /**
+ Processor Early Power On Configuration FCLK setting.
+ - <b>0: 800 MHz (ULT/ULX)</b>.
+ - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
+ - 2: 400 MHz.
+ - 3: Reserved.
+ **/
+ UINT32 FClkFrequency : 2;
+ /**
+ Enable or Disable CrashLog feature
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 CrashLogEnable : 1;
+
+ /**
+ Enable or Disable Total Memory Encryption (TME) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 TmeEnable : 1;
+
+ UINT32 DebugInterfaceEnable : 2; ///< Enable or Disable processor
debug features; 0: Disable; 1: Enable; <b>2: No Change</b>.
+ UINT32 DebugInterfaceLockEnable : 1; ///< Lock or Unlock debug interface
features; 0: Disable; <b>1: Enable</b>.
+
+ /**
+ Number of big cores in processor to enable.
+ And support up to 15 cores.
+ - 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid
CPU (MAX 16).
+ - 1: 1 core
+ - 2: 2 cores
+ - 3: 3 cores
+ **/
+ UINT32 ActiveCoreCount1 : 4;
+
+ /**
+ Enables a mailbox command to resolve rare PECI related Sx issues.
+ @note This should only be used on systems that observe PECI Sx issues.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 PeciSxReset : 1;
+
+ /**
+ Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.
+ If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit.
+ The default value <b>0: Disable</b> for CPU's
+ - 0: Disable
+ - 1: Enable
+ **/
+ UINT32 PeciC10Reset : 1; ///< @deprecated no longer used.
+
+ /**
+ Number of small cores in processor to enable.
+ And support up to 63 cores.
+ - 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid
CPU (MAX 64).
+ - 1: 1 core
+ - 2: 2 cores
+ - 3: 3 cores
+ **/
+ UINT32 ActiveSmallCoreCount : 6;
+
+ /**
+ Enable or Disable CrashLog GPRs dump
+ - <b>0: Disable</b>
+ - 1: Gprs Enabled, Smm Gprs Enabled
+ 2: Gprs Enabled, Smm Gprs Disabled
+ **/
+ UINT32 CrashLogGprs : 2;
+
+ /**
+ Enable or Disable Compute Die SSC configuration.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 ComputeDieSscEnable : 1;
+
+ /**
+ Enable or Disable Soc Die SSC configuration.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 SocDieSscEnable : 1;
+
+ /**
+ CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.
<b>0: Disabled</b> If disabled, doesn't override max-non turbo ratio.
+ **/
+ UINT8 CpuRatio;
+
+ /**
+ Number of enabled atom cores on SoC.
+ Default is set to supported core number.
+ - 0 - all core disabled
+ - 1 - enable 1 core
+ - 2 - enable 2 cores
+ - others - reserved for future use
+ **/
+ UINT8 ActiveSocNorthAtomCoreCount;
+
+ /**
+ SSC configuration value of Compute Die.
+ SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD /
100.
+ - <b>0 : invalid</b>
+ - 1 : 0.01%
+ - 2 : 0.02%
+ - 100 : 1%
+ **/
+ UINT8 ComputeDieSscValue;
+
+ /**
+ SSC configuration value of Soc Die.
+ SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD /
100.
+ - <b>0 : invalid</b>
+ - 1 : 0.01%
+ - 2 : 0.02%
+ - 100 : 1%
+ **/
+ UINT8 SocDieSscValue;
+
+ /**
+ Clock source of BCLK OC Frequency
+ - 0: SOC
+ - <b>1: CPU</b>
+ - 2: PCH
+ - 3: Ext. Clock (optional)
+ **/
+ UINT32 BclkSource : 2;
+ UINT32 RsvdBits : 30;
+ /**
+ Determine whether to keep or shutdown INF_DFX power rail. INF_DFX power is
up from cold boot.
+ - <b>0 : INF_DFX shutdown</b>
+ - 1 : INF_DFX power up </b>
+ **/
+ UINT8 InfDfxPwrEnable;
+ /**
+ Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down;
2: TDP Up.
+ **/
+ UINT8 ConfigTdpLevel;
+ UINT8 RsvdByte[2];
+ UINT32 CustomPowerLimit1;
+
+} CPU_CONFIG_LIB_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMemConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMemConfig.h
new file mode 100644
index 0000000000..c9acd48c84
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMemConfig.h
@@ -0,0 +1,63 @@
+/** @file
+ CPU Security PreMemory Config Block.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_SECURITY_PREMEM_CONFIG_H_
+#define _CPU_SECURITY_PREMEM_CONFIG_H_
+
+#define CPU_SECURITY_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuSecurityPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Security PreMemory Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 PrmrrSize; ///< PRMRR Size.<b>Software
Control: 0x0</b> 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000, 256 MB:
0x10000000, 512 MB: 0x20000000
+ UINT16 BiosSize; ///< Flash information for
BIOS Guard: BIOS Size in KB.
+ UINT8 Reserved[2]; ///< Reserved for future use
+/**
+ Enable or Disable BIOS Guard; 0: Disable; <b>1: Enable</b>.
+ - This is an optional feature and can be opted out.
+ - If this policy is set to Disabled, the policies in the BIOS_GUARD_CONFIG
will be ignored.
+ - If PeiBiosGuardLibNull is used, this policy will have no effect.
+**/
+ UINT32 BiosGuard : 1;
+ UINT32 BiosGuardToolsInterface : 1; ///< BIOS Guard Tools
Interface; <b>0: Disable</b>, 1:Enable
+/**
+ Enable or Disable Software Guard Extensions; <b>0: Disable</b>; 1: Enable.
+ - This is an optional feature and can be opted out.
+ - If this policy is set to Disabled, the policies in the CPU_SGX_CONFIG
will be ignored.
+ - If BaseSoftwareGuardLibNull is used, this policy will have no effect.
+**/
+ UINT32 EnableSgx : 1; ///< @deprecated due to
Non-POR feature.
+/**
+ Enable or Disable Trusted Execution Technology; <b>0: Disable</b>; 1:
Enable.
+ - This is an optional feature and can be opted out.
+ - If this policy is set to Disabled, the policies in the
CPU_TXT_PREMEM_CONFIG will be ignored.
+ - If PeiTxtLibNull is used, this policy will have no effect.
+**/
+ UINT32 Txt : 1;
+ UINT32 SkipStopPbet : 1; ///< <b>(Test)</b> Skip
Stop PBET Timer; <b>0: Disable</b>; 1: Enable.
+ ///
+ /// <b>(Test)</b> This policy indicates whether or not BIOS should allocate
PRMRR memory for C6DRAM power gating feature.
+ /// - 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.
+ /// - <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
+ ///
+ UINT32 EnableC6Dram : 1;
+ UINT32 ResetAux : 1; ///< <b>(Test)</b> Reset
Auxiliary content, <b>0: Disabled</b>, 1: Enabled
+ UINT32 TxtAcheckRequest : 1; ///< <b>(Test)</b>
AcheckRequest <b>0: Disabled</b>, 1: Enabled. When Enabled, it will call Acheck
regardless of crashcode value
+ UINT32 RsvdBits : 24; ///< Reserved for future
use
+} CPU_SECURITY_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_SECURITY_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/CpuRegs.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/CpuRegs.h
new file mode 100644
index 0000000000..aac4e21e2a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/CpuRegs.h
@@ -0,0 +1,63 @@
+/** @file
+ Register names for CPU registers
+
+ <b>Conventions</b>
+ - Definitions beginning with "MSR_" are MSRs
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the
registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_REGS_H_
+#define _CPU_REGS_H_
+
+///
+/// Other defines
+///
+#ifndef CPU_FEATURE_DISABLE
+#define CPU_FEATURE_DISABLE 0
+#endif
+#ifndef CPU_FEATURE_ENABLE
+#define CPU_FEATURE_ENABLE 1
+#endif
+
+//
+// Processor Definitions
+//
+#define CPUID_FULL_STEPPING 0x0000000F
+#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0
+
+#define BITS(x) (1 << (x))
+
+/**
+Notes :
+ 1. Bit position always starts at 0.
+ 2. Following macros are applicable only for Word aligned integers.
+**/
+#define BIT(Pos, Value) (1 << (Pos) & (Value))
+
+typedef UINT32 CPU_FAMILY;
+
+///
+/// Enums for CPU SKU IDs
+///
+typedef enum {
+ EnumCpuUlt = 0,
+ EnumCpuTrad,
+ EnumCpuUlx,
+ EnumCpuHalo,
+ EnumCpuUnknown
+} CPU_SKU;
+
+///
+/// Enums for CPU Generation
+///
+typedef enum {
+ EnumAdlCpu = 0,
+ EnumCpuUnknownGeneration = 255
+} CPU_GENERATION;
+#endif
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
new file mode 100644
index 0000000000..05afbf1db3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h
@@ -0,0 +1,42 @@
+/** @file
+ Header file for CpuPlatform Lib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PLATFORM_LIB_H_
+#define _CPU_PLATFORM_LIB_H_
+
+#include <Uefi.h>
+#include <CpuRegs.h>
+#include <CpuGenInfo.h>
+
+///
+/// Table to convert Seconds into equivalent MSR values
+/// This table is used for PL1, Pl2 and RATL TDP Time Window programming
+///
+extern GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mSecondsToMsrValueMapTable[][2];
+
+/**
+ Return CPU Sku
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+EFIAPI
+GetCpuSku (
+ VOID
+ );
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSize (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
new file mode 100644
index 0000000000..caa0e67bf7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h
@@ -0,0 +1,60 @@
+
+/** @file
+ CommonMsr.h
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _COMMONMSR_h
+#define _COMMONMSR_h
+#include <Base.h>
+
+/**
+ This is a Read Only MSR that is shared in the processor package and used to
+ determine the current count of enabled Cores and Threads.
+**/
+#define MSR_CORE_THREAD_COUNT 0x00000035
+
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Threadcount : 16;
+
+ /* Bits[15:0], Access Type=RO_V, default=None*/
+
+ /*
+ The Thread Count reflects the enabled threads
+ based on the factory-configured thread count and
+ the value of the RESOLVED_CORES_MASK register
+ for Server processors or the PCH Soft Reset Data
+ register for Client processors at reset time.
+ */
+ UINT32 Corecount : 16;
+
+ /* Bits[31:16], Access Type=RO_V, default=None*/
+
+ /*
+ The Core Count reflects the enabled cores based
+ on the factory-configured core count and the
+ value of the RESOLVED_CORES_MASK register for
+ Server processors or the PCH Soft Reset Data
+ register for Client processors at reset time.
+ */
+ UINT32 Rsvd32 : 32;
+
+ /* Bits[63:32], Access Type=RO, default=None*/
+
+ /* Reserved */
+
+ } Bits;
+
+ UINT32 Uint32;
+ UINT64 Uint64;
+
+} MSR_CORE_THREAD_COUNT_REGISTER;
+
+
+#endif /* _COMMONMSR_h */
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/IncludePrivate/Library/CpuInfoFruLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/IncludePrivate/Library/CpuInfoFruLib.h
new file mode 100644
index 0000000000..4095c51efb
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/IncludePrivate/Library/CpuInfoFruLib.h
@@ -0,0 +1,64 @@
+ /** @file
+ This file contains Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_INFO_FRU_LIB_H_
+#define _CPU_INFO_FRU_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <CpuRegs.h>
+#include <CpuGenInfo.h>
+#include <Register/SaRegsHostBridge.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+
+///
+/// Override table structure for cTDP and non-cTDP skus.
+/// Non-cTDP parts would have '0' data for TDP level information.
+///
+typedef struct {
+ UINTN CpuIdentifier;
+ UINT16 SkuPackageTdp;
+ UINTN MsrPowerLimit1;
+ UINTN MsrPowerLimit2;
+ UINTN CtdpUpPowerLimit1;
+ UINTN CtdpUpPowerLimit2;
+ UINTN CtdpNominalPowerLimit1;
+ UINTN CtdpNominalPowerLimit2;
+ UINTN CtdpDownPowerLimit1;
+ UINTN CtdpDownPowerLimit2;
+ UINTN MsrPowerLimit4; /// PL4 value if FVM is enabled or system
does not support FVM
+ UINTN MsrPowerLimit4DisableFvm; /// PL4 value if FVM is supported but
disabled.
+} PPM_OVERRIDE_TABLE;
+
+/**
+ Return CPU Sku
+
+ @param[in] UINT32 CpuFamilyModel
+ @param[in] UINT16 CpuDid
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+GetCpuSkuInfo (
+ IN UINT32 CpuFamilyModel,
+ IN UINT16 CpuDid
+ );
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval returns the supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSizeFru (
+ VOID
+ );
+
+#endif // _CPU_INFO_FRU_LIB_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
new file mode 100644
index 0000000000..5245a49719
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
@@ -0,0 +1,55 @@
+/** @file
+ CPU Platform Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "CpuPlatformLibrary.h"
+#include <Library/PciSegmentLib.h>
+#include <Register/SaRegsHostBridge.h>
+#include <CpuRegs.h>
+#include <Register/IgdRegs.h>
+#include <Library/CpuInfoFruLib.h>
+#include <Register/CommonMsr.h>
+#include <CpuGenInfoFruLib.h>
+#include <Pi/PiStatusCode.h>
+#include <Library/ReportStatusCodeLib.h>
+
+/**
+ Return CPU Sku
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+EFIAPI
+GetCpuSku (
+ VOID
+ )
+{
+ UINT16 CpuDid;
+ UINT32 CpuFamilyModel;
+ CPUID_VERSION_INFO_EAX Eax;
+
+ ///
+ /// Read the CPUID & DID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
+ CpuFamilyModel = Eax.Uint32 & CPUID_FULL_FAMILY_MODEL;
+ CpuDid = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS,
SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));
+
+ return GetCpuSkuInfo (CpuFamilyModel, CpuDid);
+
+}
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSize (
+ VOID
+ )
+{
+ return GetMaxPhysicalAddressSizeFru ();
+}
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h
new file mode 100644
index 0000000000..a85fe62e81
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h
@@ -0,0 +1,25 @@
+/** @file
+ Header file for Cpu Platform Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_
+#define _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/CpuLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SynchronizationLib.h>
+
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <Library/CpuPlatformLib.h>
+
+#endif
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
new file mode 100644
index 0000000000..bacef9003b
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
@@ -0,0 +1,41 @@
+## @file
+# Component description file for CPU Platform Lib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPlatformLib
+FILE_GUID = 11647130-6AA4-41A4-A3A8-5FA296ABD977
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPlatformLib
+
+
+[LibraryClasses]
+BaseLib
+BaseMemoryLib
+DebugLib
+IoLib
+PcdLib
+CpuLib
+TimerLib
+SynchronizationLib
+PciSegmentLib
+CpuInfoFruLib
+ReportStatusCodeLib
+
+[FixedPcd]
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+CpuPlatformLibrary.h
+CpuPlatformLibrary.c
--
2.36.1.windows.1
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