Reviewed-by: Sai Chaganty <rangasai.v.chaga...@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbe...@intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbe...@intel.com>; Chaganty, Rangasai V
<rangasai.v.chaga...@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desim...@intel.com>; Oram, Isaac W <isaac.w.o...@intel.com>;
Chuang, Rosen <rosen.chu...@intel.com>
Subject: [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
Adds the following library instances:
- BoardAcpiLib
- BoardInitLib
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Isaac Oram <isaac.w.o...@intel.com>
Cc: Rosen Chuang <rosen.chu...@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbe...@intel.com>
---
.../SmmAlderlakePRvpAcpiEnableLib.c | 50 +++++
.../SmmMultiBoardAcpiSupportLib.c | 88 ++++++++
.../SmmMultiBoardAcpiSupportLib.inf | 41 ++++
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 134 ++++++++++++
.../BoardInitLib/Pei/BoardPchInitPreMemLib.c | 104 +++++++++
.../BoardInitLib/Pei/BoardSaConfigPreMem.h | 73 +++++++
.../BoardInitLib/Pei/BoardSaInitPreMemLib.c | 160 ++++++++++++++
.../Library/BoardInitLib/Pei/PeiDetect.c | 62 ++++++
.../BoardInitLib/Pei/PeiInitPostMemLib.c | 100 +++++++++
.../BoardInitLib/Pei/PeiInitPreMemLib.c | 202 ++++++++++++++++++
.../Pei/PeiMultiBoardInitPostMemLib.c | 45 ++++
.../Pei/PeiMultiBoardInitPostMemLib.inf | 53 +++++
.../Pei/PeiMultiBoardInitPreMemLib.c | 89 ++++++++
.../Pei/PeiMultiBoardInitPreMemLib.inf | 149 +++++++++++++
14 files changed, 1350 insertions(+)
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
new file mode 100644
index 0000000000..8dfc04c5f5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmAlderlakePRvpAcpiEnableLib.c
@@ -0,0 +1,50 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSci Disable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..ea0f7c966b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h> #include
+<Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return AdlBoardEnableAcpi (EnableSci); }
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return AdlBoardDisableAcpi (DisableSci); }
+
+BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc = {
+ MultiBoardEnableAcpi,
+ MultiBoardDisableAcpi,
+};
+
+/**
+ The constructor function to register mBoardAcpiEnableFunc function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc); }
+
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..8a418bc8da
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,41 @@
+## @file
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PchCycleDecodingLib
+ PchPciBdfLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SmmAlderlakePRvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..fbe745ad36
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,134 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h> #include <Library/PcdLib.h>
+#include <Library/DebugLib.h> #include <Library/PmcLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegs.h> #include
+<Register/PchRegsLpc.h> #include <Register/PmcRegs.h> #include
+<Register/RtcRegs.h>
+
+/**
+ Clear Port 80h
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+
+ Disable port 60/64 SMI trap if they are enabled
+
+ Disable PM sources except power button Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status // SmiEn = IoRead32
+ (AcpiBaseAddr + R_ACPI_IO_SMI_EN); SmiEn &=
+ ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |
+ B_ACPI_IO_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+ SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS); SmiSts |=
+ B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |
+ B_ACPI_IO_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled // ULKMC =
+ MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) &
+ ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN |
+ B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN |
+ B_LPC_CFG_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+ IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); }
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..13ad444f8b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardPchInitPreMemLib.c
@@ -0,0 +1,104 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory
Init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h> #include
+<Include/PlatformBoardId.h> #include <PlatformBoardConfig.h> #include
+<Library/PcdLib.h> #include <PlatformBoardId.h> #include
+<Library/PchInfoLib.h>
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memory
phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ )
+{
+ PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];
+ UINT32 Index;
+ PCIE_CLOCKS_USAGE *PcieClocks;
+
+ PcieClocks = NULL;
+
+ //
+ //The default clock assignment will be NOT_USED, which corresponds to
PchClockUsageNotUsed. This will prevent clocks drawing Power by default.
+ //If Platform code doesn't contain port-clock map for a given board, the
clocks will be NOT_USED, preventing PCIe devices not to operate.
+ //To prevent this, remember to provide port-clock map for every board.
+ //
+ for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported = TRUE;
+ Clock[Index].PcieClock.ClockUsage = NOT_USED; }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0) /// For LP, Set 0 -
+ 5 /// For H, Set 0 - 15 /// Note that if GbE is enabled, ClkReq
+ assigned to GbE will not be available for Root Port.
+ ///
+
+ PcieClocks = PcdGetPtr(VpdPcdPcieClkUsageMap); if (PcieClocks ==
+ NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Clock[0].PcieClock.ClockUsage = PcieClocks->ClockUsage[0];
+ Clock[1].PcieClock.ClockUsage = PcieClocks->ClockUsage[1];
+ Clock[2].PcieClock.ClockUsage = PcieClocks->ClockUsage[2];
+ Clock[3].PcieClock.ClockUsage = PcieClocks->ClockUsage[3];
+ Clock[4].PcieClock.ClockUsage = PcieClocks->ClockUsage[4];
+ Clock[5].PcieClock.ClockUsage = PcieClocks->ClockUsage[5];
+ Clock[6].PcieClock.ClockUsage = PcieClocks->ClockUsage[6];
+ Clock[7].PcieClock.ClockUsage = PcieClocks->ClockUsage[7];
+ Clock[8].PcieClock.ClockUsage = PcieClocks->ClockUsage[8];
+ Clock[9].PcieClock.ClockUsage = PcieClocks->ClockUsage[9];
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+**/
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+
+ return;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..c79555cde8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardSaConfigPreMem.h
@@ -0,0 +1,73 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/BoardConfigLib.h>
+
+#define SA_MRC_MAX_RCOMP_TARGETS (5)
+
+//
+// Reference RCOMP resistors on motherboard - MRC will set
+automatically // GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
+AdlPRcompResistorZero = 0;
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - MRC
+will set automatically // GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
+RcompTargetAdlP[SA_MRC_MAX_RCOMP_TARGETS] = { 0, 0, 0, 0, 0 };
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side //
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapAdlP[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to
package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ },
+ // Channel 1:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to
package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ }
+};
+
+//
+// Display DDI settings for Adl-P Ddr5 Rvp Edp + DP //
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mAdlPDdr5RvpDisplayDdiConfig[16] = {
+
DdiPortEdp, // DDI Port A Config : DdiPortDisabled = No LFP is Connected,
DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+
DdiPortDisabled, // DDI Port B Config : DdiPortDisabled = No LFP is Connected,
DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+
DdiHpdDisable, // DDI Port A HPD : DdiHpdDisable = Disable, DdiHpdEnable =
Enable HPD
+
DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable =
Enable HPD
+
DdiHpdDisable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable =
Enable HPD
+
DdiHpdDisable, // DDI Port 1 HPD : DdiHpdDisable = Disable, DdiHpdEnable =
Enable HPD
+
DdiHpdDisable, // DDI Port 2 HPD : DdiHpdDisable = Disable, DdiHpdEnable =
Enable HPD
+
DdiHpdDisable, // DDI Port 3 HPD : DdiHpdDisable = Disable, DdiHpdEnable =
Enable HPD
+
DdiHpdDisable, // DDI Port 4 HPD : DdiHpdDisable = Disable, DdiHpdEnable =
Enable HPD
+
DdiDisable, // DDI Port A DDC : DdiDisable = Disable, DdiDdcEnable =
Enable DDC
+
DdiDisable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable =
Enable DDC
+
DdiDisable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable =
Enable DDC
+
DdiDisable, // DDI Port 1 DDC : DdiDisable = Disable, DdiDdcEnable =
Enable DDC
+
DdiDisable, // DDI Port 2 DDC : DdiDisable = Disable, DdiDdcEnable =
Enable DDC
+
DdiDisable, // DDI Port 3 DDC : DdiDisable = Disable, DdiDdcEnable =
Enable DDC
+
DdiDisable // DDI Port 4 DDC : DdiDisable = Disable, DdiDdcEnable =
Enable DDC
+};
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..e42c8fb5f8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardSaInitPreMemLib.c
@@ -0,0 +1,160 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory
init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include <Library/CpuPlatformLib.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ )
+{
+ PcdSet8S (PcdSaMiscUserBd, 6);
+ return;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory
phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPMrcConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BOOLEAN ExternalSpdPresent;
+ MRC_DQS *MrcDqs;
+ MRC_DQ *MrcDq;
+ SPD_DATA *SpdData;
+
+ BoardId = PcdGet16(PcdBoardId);
+
+ // SPD is the same size for all boards PcdSet16S (PcdMrcSpdDataSize,
+ 512);
+
+ ExternalSpdPresent = PcdGetBool (PcdSpdPresent);
+
+ // Assume internal SPD is used
+ PcdSet8S (PcdMrcSpdAddressTable0, 0); PcdSet8S
+ (PcdMrcSpdAddressTable1, 0); PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0); PcdSet8S
+ (PcdMrcSpdAddressTable4, 0); PcdSet8S (PcdMrcSpdAddressTable5, 0);
+ PcdSet8S (PcdMrcSpdAddressTable6, 0); PcdSet8S
+ (PcdMrcSpdAddressTable7, 0); PcdSet8S (PcdMrcSpdAddressTable8, 0);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0); PcdSet8S
+ (PcdMrcSpdAddressTable10, 0); PcdSet8S (PcdMrcSpdAddressTable11, 0);
+ PcdSet8S (PcdMrcSpdAddressTable12, 0); PcdSet8S
+ (PcdMrcSpdAddressTable13, 0); PcdSet8S (PcdMrcSpdAddressTable14, 0);
+ PcdSet8S (PcdMrcSpdAddressTable15, 0);
+
+ // Check for external SPD presence
+ if (ExternalSpdPresent) {
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
+ PcdSet8S (PcdMrcSpdAddressTable8, 0xA4);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0xA6);
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Setting the default DQ Byte Map. It may be overriden to board specific
settings below.
+ PcdSet32S (PcdMrcDqByteMap, (UINTN) DqByteMapAdlP); PcdSet16S
+ (PcdMrcDqByteMapSize, sizeof (DqByteMapAdlP));
+
+ // ADL uses the same RCOMP resistors for all DDR types PcdSet32S
+ (PcdMrcRcompResistor, (UINTN) AdlPRcompResistorZero);
+
+ // Use default RCOMP target values for all boards PcdSet32S
+ (PcdMrcRcompTarget, (UINTN) RcompTargetAdlP);
+
+ // Default is NIL
+ PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE); PcdSetBoolS
+ (PcdMrcDqPinsInterleaved, FALSE);
+
+ // DqsMapCpu2Dram is the same size for all boards PcdSet16S
+ (PcdMrcDqsMapCpu2DramSize, sizeof (MRC_DQS)); // DqMapCpu2Dram is the
+ same size for all boards PcdSet16S (PcdMrcDqMapCpu2DramSize, sizeof
+ (MRC_DQ));
+ PcdSet8S (PcdMrcLp5CccConfig, 0x0);
+
+ // CPU-DRAM DQ mapping
+ MrcDq = PcdGetPtr (VpdPcdMrcDqMapCpu2Dram); if (MrcDq != NULL) {
+ PcdSet32S (PcdMrcDqMapCpu2Dram, (UINTN)MrcDq->DqMapCpu2Dram); }
+
+ // CPU-DRAM DQS mapping
+ MrcDqs = PcdGetPtr (VpdPcdMrcDqsMapCpu2Dram); if (MrcDqs != NULL) {
+ PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN)MrcDqs->DqsMapCpu2Dram); }
+
+ // DRAM SPD Data
+ SpdData = PcdGetPtr (VpdPcdMrcSpdData); if (SpdData != NULL) {
+ if (SpdData->OverrideSpd == TRUE) {
+ PcdSet32S (PcdMrcSpdData, (UINTN)SpdData->SpdData);
+ }
+ }
+
+ return;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ BoardId = PcdGet16 (PcdBoardId);
+
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "DDI Configuration ADLP Edp DP\n"));
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN)
mAdlPDdr5RvpDisplayDdiConfig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof
(mAdlPDdr5RvpDisplayDdiConfig));
+ break;
+ default:
+ break;
+ }
+
+ return;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
new file mode 100644
index 0000000000..5ad8e56f4d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiDetect.c
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/BoardConfigLib.h>
+
+BOOLEAN
+IsAdlP (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16 (PcdBoardId);
+ if (BoardId == 0) {
+ DEBUG ((DEBUG_INFO, "Let's get Board information first ...\n"));
+ GetBoardConfig ();
+ BoardId = PcdGet16 (PcdBoardId);
+ }
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "AlderLake P Board detected\n"));
+
+ // set sku type to ADL P
+ PcdSet8S (PcdSkuType, AdlPSkuType);
+ return TRUE;
+ break;
+ default:
+ return FALSE;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ )
+{
+ UINTN SkuId;
+ SkuId = 0;
+
+ if (LibPcdGetSku () != 0) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_INFO, "AlderLakeP Board Detection Callback\n"));
+
+ if (IsAdlP ()) {
+ SkuId = (UINTN) (PcdGet16 (PcdBoardBomId) << 16) | (PcdGet16 (PcdBoardRev)
<< 8) | (PcdGet16 (PcdBoardId));
+ LibPcdSetSku (SkuId);
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ }
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
new file mode 100644
index 0000000000..51201bb300
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiInitPostMemLib.c
@@ -0,0 +1,100 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Library/BoardConfigLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PchInfoLib.h>
+#include <Library/HobLib.h>
+
+
+
+/**
+ Alderlake P boards configuration init function for PEI post memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInit (
+ VOID
+ )
+{
+ UINT16 GpioCount;
+ UINTN Size;
+ EFI_STATUS Status;
+ GPIO_INIT_CONFIG *GpioTable;
+ //
+ // GPIO Table Init
+ //
+ Status = EFI_SUCCESS;
+ GpioCount = 0;
+ Size = 0;
+ GpioTable = NULL;
+ //
+ // GPIO Table Init
+ //
+ //
+ // GPIO Table Init, Update PostMem GPIO table to PcdBoardGpioTable
+ //
+ GpioTable = (GPIO_INIT_CONFIG *)PcdGetPtr(VpdPcdBoardGpioTable);
+
+ GetGpioTableSize (GpioTable, &GpioCount); // // Increase GpioCount
+ for the zero terminator.
+ //
+ GpioCount ++;
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG)); Status =
+ PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable); ASSERT_EFI_ERROR
+ (Status);
+
+ return Status;
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); }
+
+/**
+ Configure GPIO, TouchPanel, HDA, PMC, TBT etc.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ AdlPInit ();
+ GpioInit (PcdGetPtr (PcdBoardGpioTable));
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
new file mode 100644
index 0000000000..0b7db476a1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiInitPreMemLib.c
@@ -0,0 +1,202 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BiosIdLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/PeiLib.h>
+#include <Guid/MemoryOverwriteControl.h> #include
+<PlatformBoardConfig.h> #include <Library/PchCycleDecodingLib.h>
+#include <Register/PmcRegs.h> #include <Library/PmcLib.h> #include
+<Ppi/ReadOnlyVariable2.h> #include <Library/PeiServicesLib.h> #include
+<Library/GpioLib.h> #include <Library/BoardConfigLib.h> #include
+<Library/TimerLib.h> #include <PlatformBoardId.h> #include
+<Library/IoLib.h> #include <Pins/GpioPinsVer2Lp.h> #include
+<Library/PchInfoLib.h>
+
+/**
+ Get Vpd binary address
+
+ Parse through each FV for VPD FFS file and return the address
+
+ @retval Address on VPD FFS detection else returns 0
+
+**/
+UINTN
+EFIAPI
+GetVpdFfsAddress (
+ )
+{
+ EFI_STATUS Status;
+ VOID *Address;
+ UINTN Instance;
+ EFI_PEI_FV_HANDLE VolumeHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+
+ Address = NULL;
+
+ VolumeHandle = NULL;
+ Instance = 0;
+ while (TRUE) {
+ //
+ // Traverse all firmware volume instances.
+ //
+ Status = PeiServicesFfsFindNextVolume (Instance, &VolumeHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ FileHandle = NULL;
+ Status = PeiServicesFfsFindFileByName (&gVpdFfsGuid, VolumeHandle,
&FileHandle);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Search RAW section.
+ //
+ Status = PeiServicesFfsFindSectionData (EFI_SECTION_RAW, FileHandle,
&Address);
+ if (!EFI_ERROR (Status)) {
+ return (UINTN)Address;
+ }
+ }
+
+ //
+ // Search the next volume.
+ //
+ Instance++;
+ }
+
+ DEBUG ((DEBUG_ERROR, " PEI get VPD address: %r\n", EFI_NOT_FOUND));
+ return 0;
+}
+
+/**
+ Alderlake P boards configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInitPreMem (
+ VOID
+ )
+{
+ UINTN VpdBaseAddress;
+
+ VpdBaseAddress = (UINTN) PcdGet64 (PcdVpdBaseAddress64); DEBUG
+ ((DEBUG_INFO, "VpdFfsAddress: %x\n", VpdBaseAddress)); if
+ (VpdBaseAddress == 0) {
+ VpdBaseAddress= (UINTN) GetVpdFfsAddress();
+ PcdSet64S (PcdVpdBaseAddress64,VpdBaseAddress);
+ DEBUG ((DEBUG_INFO, "VpdFfsAddress updated: %x\n",
+ VpdBaseAddress)); } PcdSet32S (PcdStackBase, PcdGet32
+ (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize) - (PcdGet32
+ (PcdFspTemporaryRamSize) + PcdGet32 (PcdFspReservedBufferSize)));
+ PcdSet32S (PcdStackSize, PcdGet32 (PcdFspTemporaryRamSize));
+
+ return EFI_SUCCESS;
+}
+
+
+VOID
+AdlPMrcConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ );
+
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ );
+
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ );
+
+
+/**
+ A hook for board-specific initialization prior to memory initialization.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitBeforeMemoryInit\n"));
+
+ AdlPInitPreMem ();
+
+ AdlPGpioGroupTierInit ();
+
+ AdlPMrcConfigInit ();
+ AdlPSaMiscConfigInit ();
+ Status = AdlPRootPortClkInfoInit ();
+ AdlPSaDisplayConfigInit ();
+ if (PcdGetPtr (PcdBoardGpioTableEarlyPreMem) != 0) {
+ GpioInit (PcdGetPtr (PcdBoardGpioTableEarlyPreMem));
+
+ MicroSecondDelay (15 * 1000); // 15 ms Delay } // Configure GPIO
+ Before Memory GpioInit (PcdGetPtr (PcdBoardGpioTablePreMem));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This board service initializes board-specific debug devices.
+
+ @retval EFI_SUCCESS Board-specific debug initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardDebugInit\n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This board service detects the boot mode.
+
+ @retval EFI_BOOT_MODE The boot mode.
+**/
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardBootModeDetect\n"));
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..aa9809d126
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,45 @@
+/** @file
+ PEI Multi-Board Initialization in Post-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+
+BOARD_POST_MEM_INIT_FUNC mAdlPBoardInitFunc = {
+ AdlPBoardInitBeforeSiliconInit,
+ NULL,
+};
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ SkuType = PcdGet8 (PcdSkuType);
+
+ if (SkuType==AdlPSkuType) {
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardPostMemInit (&mAdlPBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..a4dbc9294d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Component information file for Alderlake Multi-Board Initialization in PEI
post memory phase.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitLib
+ FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PciSegmentLib
+ GpioLib
+ HobLib
+ BoardConfigLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Sources]
+ PeiInitPostMemLib.c
+ PeiMultiBoardInitPostMemLib.c
+
+[Pcd]
+ # Board GPIO Table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+
+ # TPM interrupt
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES
+ #Misc Config
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..fa45e86ac2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,89 @@
+/** @file
+ PEI Multi-Board Initialization in Pre-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h>
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+BOARD_DETECT_FUNC mAdlPBoardDetectFunc = {
+ AdlPMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mAdlPBoardPreMemInitFunc = {
+ AdlPBoardDebugInit,
+ AdlPBoardBootModeDetect,
+ AdlPBoardInitBeforeMemoryInit,
+ NULL, // BoardInitAfterMemoryInit
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ DEBUG ((DEBUG_INFO, " In AdlPMultiBoardDetect \n"));
+
+ AdlPBoardDetect ();
+
+ SkuType = PcdGet8 (PcdSkuType);
+ if (SkuType==AdlPSkuType) {
+ RegisterBoardPreMemInit (&mAdlPBoardPreMemInitFunc);
+ } else {
+ DEBUG ((DEBUG_WARN,"Not a Valid Alderlake P Board\n"));
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mAdlPBoardDetectFunc); }
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..ea2b64050d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,149 @@
+## @file
+# Component information file for PEI Alderlake P Board Init Pre-Mem
+Library #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitPreMemLib
+ FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PeiLib
+ BoardConfigLib
+ PchInfoLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Sources]
+ PeiInitPreMemLib.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiDetect.c
+ BoardSaInitPreMemLib.c
+ BoardPchInitPreMemLib.c
+
+[Pcd]
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15
+
+ #MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+
+ #Board Information
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent
+ gBoardModuleTokenSpaceGuid.PcdBoardRev
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdStackBase
+ gBoardModuleTokenSpaceGuid.PcdStackSize
+
+ #SA GPIO Config
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+
+
+ # WWAN Full Card Power Off and reset pins
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ##
PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem ##
PRODUCES
+
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64 ## CONSUMES
+
+[Guids]
+ gFspNonVolatileStorageHobGuid
+ gEfiMemoryOverwriteControlDataGuid
+ gVpdFfsGuid
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#107468): https://edk2.groups.io/g/devel/message/107468
Mute This Topic: https://groups.io/mt/100494311/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
