Adds the following libraries - BasePlatformHookLib - DxeAcpiGnvsInitLib - PeiBoardConfigLib - PeiGetFvInfoLib - PeiReportFvLib - SmmSpiFlashCommonLib
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> Cc: Isaac Oram <isaac.w.o...@intel.com> Cc: Rosen Chuang <rosen.chu...@intel.com> Signed-off-by: Saloni Kasbekar <saloni.kasbe...@intel.com> --- .../BasePlatformHookLib/BasePlatformHookLib.c | 38 + .../BasePlatformHookLib.inf | 48 + .../DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c | 62 + .../DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf | 34 + .../PeiBoardConfigLib/PeiBoardConfigLib.c | 252 ++++ .../PeiBoardConfigLib/PeiBoardConfigLib.inf | 73 ++ .../Library/PeiBoardConfigLib/PeiSpdTables.c | 1041 +++++++++++++++++ .../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89 ++ .../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 + .../Library/PeiReportFvLib/PeiReportFvLib.c | 372 ++++++ .../Library/PeiReportFvLib/PeiReportFvLib.inf | 78 ++ .../SmmSpiFlashCommonLib.inf | 52 + .../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++++ .../SpiFlashCommonSmmLib.c | 64 + 14 files changed, 2452 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..cccb1e18cc --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -0,0 +1,38 @@ +/** @file + Platform Hook Library instances + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Uefi/UefiBaseType.h> +#include <Library/PchCycleDecodingLib.h> + + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function does + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succeeded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + + // + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. + // + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); + + return RETURN_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..19458e7724 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf @@ -0,0 +1,48 @@ +### @file +# Platform Hook Library instance for Alderlake Mobile/Desktop CRB. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BasePlatformHookLib + FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = PlatformHookLib +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciSegmentLib + PciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES + +[FixedPcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + +[Sources] + BasePlatformHookLib.c diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c new file mode 100644 index 0000000000..3aef72ea52 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c @@ -0,0 +1,62 @@ +/** @file + Acpi Gnvs Init Library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Uefi.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/PlatformNvsArea.h> +#include <Library/DxeAcpiGnvsInitLib.h> + +/** +@brief + Global NVS initialize. + + @param[in] PlatformNvsAreaPtr - Pointer of global NVS area + + @retval EFI_SUCCESS - Allocate Global NVS completed. + @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for PlatformNvsAreaProtocol. +**/ +EFI_STATUS +EFIAPI +AcpiGnvsInit ( + IN OUT VOID **PlatformNvsAreaPtr + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + PLATFORM_NVS_AREA_PROTOCOL *PlatformNvsAreaProtocol; + + Pages = EFI_SIZE_TO_PAGES (sizeof (PLATFORM_NVS_AREA)); + Address = 0xffffffff; // allocate address below 4G. + + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + + *PlatformNvsAreaPtr = (VOID *) (UINTN) Address; + SetMem (*PlatformNvsAreaPtr, sizeof (PLATFORM_NVS_AREA), 0); + + // + // PlatformNvsAreaProtocol default value init here... + // + PlatformNvsAreaProtocol = (PLATFORM_NVS_AREA_PROTOCOL *) &Address; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf new file mode 100644 index 0000000000..f9ec542f50 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf @@ -0,0 +1,34 @@ +### @file +# Component description file for the DxeAcpiGnvsInitLib +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxeAcpiGnvsInitLib + FILE_GUID = 9972077E-00AA-4F66-8CDA-E53CBD74A2F9 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = DxeAcpiGnvsInitLib + +[LibraryClasses] + BaseLib + DebugLib + IoLib + BaseMemoryLib + UefiBootServicesTableLib + +[Packages] + MdePkg/MdePkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[Sources] + DxeAcpiGnvsInitLib.c + +[Pcd] + # gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES + # gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c new file mode 100644 index 0000000000..7b041e9315 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c @@ -0,0 +1,252 @@ +/** @file + Implementation of PeiBoardConfigLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <PiPei.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/PostCodeLib.h> +#include <Library/TimerLib.h> + +#include <Library/GpioLib.h> + +#include <PlatformBoardType.h> +#include <PlatformBoardId.h> +#include <PlatformBoardConfig.h> +#include <Ppi/ReadOnlyVariable2.h> +#include <Library/PeiServicesLib.h> +#include <Library/PmcLib.h> +#include <Library/BoardConfigLib.h> + + + +VOID +EFIAPI +InternalUpdateRvpBoardConfig ( + IN OUT UINT16 BoardId + ) +{ + UINT8 BoardType; + UINT8 PlatformType; + UINT8 PlatformFlavor; + + // + // Update Board Type/Platform Type/Platform Flavor + // + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + BoardType = BoardTypeRvp; + PlatformType = TypeUltUlx; + PlatformFlavor = FlavorMobile; + if(PcdSet64S (PcdAcpiDefaultOemTableId, ACPI_OEM_TABLE_ID_ADL_P_M) != EFI_SUCCESS) + { + DEBUG ((DEBUG_INFO, "Set PcdAcpiDefaultOemTableId error!!!\n")); + } + break; + + default: + BoardType = BoardTypeRvp; + PlatformType = TypeUnknown; + PlatformFlavor = FlavorUnknown; + break; + } + + PcdSet8S (PcdBoardType, BoardType); + PcdSet8S (PcdPlatformType, PlatformType); + PcdSet8S (PcdPlatformFlavor, PlatformFlavor); + + DEBUG ((DEBUG_INFO, "PcdAcpiDefaultOemTableId is 0x%llX\n", PcdGet64 (PcdAcpiDefaultOemTableId))); +} + +/** + Procedure to detect current board HW configuration. + +**/ +VOID +GetBoardConfig ( + VOID + ) +{ + UINT16 BoardId; + + // + // Get Platform Info and fill the PCD + // + BoardId = BoardIdAdlPDdr5Rvp; + PcdSet8S (PcdBoardType, BoardTypeMax); + PcdSet16S (PcdBoardId, BoardId); + // + // update RVP board config + // + InternalUpdateRvpBoardConfig (BoardId); + + DEBUG ((DEBUG_INFO, "Platform Information:\n")); + DEBUG ((DEBUG_INFO, "PlatformType: %x\n", PcdGet8 (PcdPlatformType))); + DEBUG ((DEBUG_INFO, "PlatformFlavor: %x\n", PcdGet8 (PcdPlatformFlavor))); + DEBUG ((DEBUG_INFO, "BoardID: 0x%x\n", BoardId)); + DEBUG ((DEBUG_INFO, "BoardType: %x\n", PcdGet8 (PcdBoardType))); + +} + +/** + Count the number of GPIO settings in the Table. + + @param[in] GpioTable The pointer of GPIO config table + @param[out] GpioCount The number of GPIO config entries +**/ +VOID +GetGpioTableSize ( + GPIO_INIT_CONFIG *GpioTable, + OUT UINT16 *GpioCount + ) +{ + *GpioCount = 0; + if(GpioTable != NULL) { + while (GpioTable[*GpioCount].GpioPad != 0 && *GpioCount < MAX_GPIO_PINS) { + DEBUG ((DEBUG_INFO, "GpioTable[%d]->GpioPad = %x \n", *GpioCount, GpioTable[*GpioCount].GpioPad)); + (*GpioCount) ++; + } + } else { + DEBUG ((DEBUG_INFO, "GpioTable is NULL\n")); + } + DEBUG ((DEBUG_INFO, "GetGpioTableSize() GpioCount = %d\n", *GpioCount)); +} + +/** +Configure GPIO Table setting to PcdBoardGpioTablePreMem && PcdBoardGpioTable + +@param[in] GpioTable The pointer of GPIO config table +@param[in] IsPostMem Is call from PostMem/PreMem + True - PostMem, False - PreMem +**/ +VOID +ConfigureGpioTabletoPCD( + IN GPIO_INIT_CONFIG *GpioTable, + IN UINT16 IsPostMem + ) +{ + UINT16 GpioCount = 0; + UINTN Size = 0; + EFI_STATUS Status = EFI_SUCCESS; + BOOLEAN DisableVpdGpioTable = FALSE; + + DEBUG ((DEBUG_INFO, "ConfigureGpioTabletoPCD() Start\n")); + + DisableVpdGpioTable = (BOOLEAN) PcdGetBool (PcdDisableVpdGpioTable); + DEBUG((DEBUG_INFO, "PcdDisableVpdGpioTable = %d\n", DisableVpdGpioTable)); + if (!DisableVpdGpioTable) { + if (GpioTable != NULL) { + GetGpioTableSize (GpioTable, &GpioCount); + if (GpioCount) { + if (IsPostMem == POST_MEM) { // Post Mem GPIO Configuration + if (GpioCount >= MAX_GPIO_PINS) { + DEBUG ((DEBUG_ERROR, "GpioTable entries exceeds limit, Configure only MAX_GPIO_PINS Pins.\n")); + GpioCount = MAX_GPIO_PINS; + } + DEBUG ((DEBUG_INFO, "GpioTable Count = %d\n", GpioCount)); + Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG)); + Status = PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable); + } else if (IsPostMem == PRE_MEM) { // Pre Mem GPIO Configuration + if (GpioCount >= MAX_PRE_MEM_GPIO_PINS) { + DEBUG ((DEBUG_ERROR, "PreMem GpioTable entries exceeds limit, Configure only MAX_PRE_MEM_GPIO_PINS Pins.\n")); + GpioCount = MAX_PRE_MEM_GPIO_PINS; + } + DEBUG ((DEBUG_INFO, "GpioTable Count = %d\n", GpioCount)); + Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG)); + Status = PcdSetPtrS (PcdBoardGpioTablePreMem, &Size, GpioTable); + } else if (IsPostMem == EARLY_PRE_MEM) { // Pre Mem GPIO Configuration + if (GpioCount >= MAX_PRE_MEM_GPIO_PINS) { + DEBUG((DEBUG_ERROR, "EarlyPreMem GpioTable entries exceeds limit, Configure only MAX_PRE_MEM_GPIO_PINS Pins.\n")); + GpioCount = MAX_PRE_MEM_GPIO_PINS; + } + DEBUG((DEBUG_INFO, "EarlyPreMem GpioTable Count = %d\n", GpioCount)); + Size = (UINTN)(GpioCount * sizeof(GPIO_INIT_CONFIG)); + Status = PcdSetPtrS(PcdBoardGpioTableEarlyPreMem, &Size, GpioTable); + } + ASSERT_EFI_ERROR (Status); + } else { + DEBUG ((DEBUG_INFO, "GpioTable is Empty\n")); + } + } else { + DEBUG ((DEBUG_INFO, "GpioTable is NULL\n")); + } + } else { + DEBUG ((DEBUG_INFO, "PcdDisableVpdGpioTable is TRUE, GPIO Tables will be updated by PCT PEIM \n")); + } + + DEBUG ((DEBUG_INFO, "ConfigureGpioTabletoPCD() End\n")); +} + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries +**/ +STATIC +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioTable, + IN UINT16 GpioTableCount + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + Status = GpioConfigurePads (GpioTableCount, GpioTable); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +/** + Configure GPIO Before Memory is initialized. + + @param[in] GpioTable Pointer to Gpio table +**/ +VOID +GpioInit ( + IN GPIO_INIT_CONFIG *GpioTable + ) +{ + UINT16 GpioCount; + + if (GpioTable != 0) { + GpioCount = 0; + GetGpioTableSize (GpioTable, &GpioCount); + if (GpioCount != 0) { + ConfigureGpio ((VOID *) GpioTable, (UINTN) GpioCount); + } + } +} + +/** + Update Cpu Xhci Port Enable Map PCD from SaSetup data. + +**/ +VOID +EFIAPI +TcssUpdateCpuXhciPortEnableMapPcd ( + VOID + ) +{ + UINT8 PortEnableMask; + UINT8 PortEnableMap; + + DEBUG ((DEBUG_INFO, "[TCSS] TcssUpdateCpuXhciPortEnableMapPcd: Start\n")); + PortEnableMask = 0x0F; // Enable Mask for All 4 CPU USB Port. + PortEnableMap = PcdGet8 (PcdCpuXhciPortSupportMap); // Get Board Capability Map set Cpu Xhci Port. + + + DEBUG ((DEBUG_INFO, "[TCSS] Cpu Usb Port Enable Mask is = 0x%x\n", PortEnableMask)); + PortEnableMap &= PortEnableMask; // Apply the Mask calculated from SaSetup Data. + DEBUG ((DEBUG_INFO, "[TCSS] Cpu Usb Port Enable Map in Post-Mem is = 0x%x\n", PortEnableMap)); + PcdSet8S (PcdCpuUsb30PortEnable, PortEnableMap); + DEBUG ((DEBUG_INFO, "[TCSS] TcssUpdateCpuXhciPortEnableMapPcd: End\n")); +} + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf new file mode 100644 index 0000000000..4e3f3d375b --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf @@ -0,0 +1,73 @@ +### @file +# Component information file for BaseBoardConfigLib. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardConfigLib + FILE_GUID = AA9812A8-1BA6-40AD-A846-50D0BC29C38C + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardConfigLib|PEIM + +[LibraryClasses] + DebugLib + PcdLib + PostCodeLib + TimerLib + PeiServicesLib + PmcLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiBoardConfigLib.c + PeiSpdTables.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardId ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardBomId ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardRev ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSpdPresent ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardType ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPlatformType ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## PRODUCES ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPlatformGeneration ## CONSUMES + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdDisplayId ## PRODUCES ## CONSUMES + + # Cpu USB XHCI Port Enable Mapping + gBoardModuleTokenSpaceGuid.PcdCpuXhciPortSupportMap + gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES + gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES + +[Guids] + gBoardInfoVariableGuid + +[Depex] + gEfiPeiReadOnlyVariable2PpiGuid \ No newline at end of file diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c new file mode 100644 index 0000000000..37cd660014 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c @@ -0,0 +1,1041 @@ +/** @file + SPD tables for ADL boards. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// LPDDR4 200b +// Samsung K4F6E304Hx-MGCJ +// or Hynix H9HCNNNBUUxLHR-NMx +// or Micron MT53B512M32D2NP-053 +// 3733, 32-34-34-79 +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4Ddp8Gb200bSpd[] = { + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x11, ///< 1 SPD Revision 1.1 + 0x10, ///< 2 DRAM Type: LPDDR4 SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density + 0x19, ///< 5 15 Rows, 10 Columns + 0x91, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1 + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x00, ///< 16 Signal Loading: not specified + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733) + 0x0F, ///< 19 tCKAVGmax = 1.875 ns + 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20 + 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32 + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns + 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0xA0, ///< 29 tRFCab = 180 ns (8 Gb dual-channel die) + 0x05, ///< 30 tRFCab MSB + 0xD0, ///< 31 tRFCpb = 90 ns (8 Gb dual-channel die) + 0x02, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0x92, ///< 123 FTB for tAAmin = 17.14 ns + 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns + 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (LPDDR4-3733) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x20, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +// LPDDR4X 556b +// Micron MT53D512M64D4RQ-046 WT:E +// 4266 +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp4Gb556bSpd[] = { + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x11, ///< 1 SPD Revision 1.1 + 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density + 0x21, ///< 5 16 Row bits, 10 Column bits + 0xB9, ///< 6 Non-Monolithic DRAM Device, 4 dies, 2 Channels per die, Signal Loading not specified + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x00, ///< 16 Signal Loading: Not Specific + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x04, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733) + 0x0F, ///< 19 tCKAVGmax = 1.875 ns + 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20 + 0x05, ///< 22 CAS Latencies supported (Third Byte) : 32 + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x87, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns + 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0xC0, ///< 29 tRFCab = 280 ns (8 Gb single-channel die) + 0x08, ///< 30 tRFCab MSB + 0x60, ///< 31 tRFCpb = 140 ns (8 Gb single-channel die) + 0x04, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xE5, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns) + 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns) + 0xE1, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733) + 0x85, ///< 126 CRC A + 0x85, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x56, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +// LPDDR4X 432b +// Samsung K3UH7H70MM-JGCJ +// 3733, 32-34-34-79 +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp16Gb432bSpd[] = { + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x11, ///< 1 SPD Revision 1.1 + 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x16, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density + 0x21, ///< 5 16 Row bits, 10 Column bits + 0xB4, ///< 6 Non-Monolithic DRAM Device, 4 dies, 2 Channels per die, Signal Loading not specified + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733) + 0x0F, ///< 19 tCKAVGmax = 1.875 ns + 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20 + 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32 + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns + 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0xC0, ///< 29 tRFCab = 280 ns (16 Gb dual-channel die) + 0x08, ///< 30 tRFCab MSB + 0x60, ///< 31 tRFCpb = 140 ns (16 Gb dual-channel die) + 0x04, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0x92, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns) + 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns) + 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x43, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x80, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0xCE, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +// LPDDR4X 556b +// Micron MT53D1G64D8SQ-046 +// 4266 +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xOdp8Gb556bSpd[] = { + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x11, ///< 1 SPD Revision 1.1 + 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x1B, ///< 4 8 Banks, no bank groups, 6 Gb SDRAM density + 0x21, ///< 5 15 Rows, 10 Columns + 0xF8, ///< 6 Non-Monolithic DRAM Device, 8 die, 4 Channels per package, Signal Loading Matrix 1 + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x00, ///< 16 Signal Loading: Not Specific + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733) + 0x0F, ///< 19 tCKAVGmax = 1.875 ns + 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20 + 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32 + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns + 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0xC0, ///< 29 tRFCab = 280 ns (8 Gb single-channel die) + 0x08, ///< 30 tRFCab MSB + 0x60, ///< 31 tRFCpb = 140 ns (8 Gb single-channel die) + 0x04, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0x92, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns) + 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns) + 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x56, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4Ddp16Gb200b1rSpd[] = { + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x10, ///< 1 SPD Revision 1.0 + 0x11, ///< 2 DRAM Type: LPDDR4X SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density + 0x19, ///< 5 15 Rows, 10 Columns + 0x95, ///< 6 Non-Monolithic DRAM Device, 2 die, 2 Channels per package, Signal Loading Matrix 1 + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x04, ///< 18 tCKAVGmin = 0.469 ns (LPDDR4-4267) + 0xFF, ///< 19 tCKAVGmax = 32.002 ns + 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16 + 0x00, ///< 22 CAS Latencies supported (Third Byte) : + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns + 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die) + 0x06, ///< 30 tRFCab MSB + 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die) + 0x02, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0x00, ///< 123 FTB for tAAmin = 17.5 ns + 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns + 0xE1, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x55, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +// LPDDR5 496b 12Gb die, QDP 1x16 +// Samsung K3LK2K20BM-BGCN +// 5500, ??-??-??-?? +// 16 Banks, 4 bank groups, 12Gb SDRAM density +// 16 Row bits, 10 Column bits +// Non-Monolithic DRAM Device, 4 dies, 4 Channels per die, +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr5xQdp12Gb496bSpd[] = { + // ************************************ + // Placeholder need correct SPD for LP5 + // ************************************ + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x10, ///< 1 SPD Revision 1.0 + 0x13, ///< 2 DRAM Type: LPDDR5 SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x88, ///< 4 8 Banks, no bank groups, 12 Gb SDRAM density + 0x29, ///< 5 17 Rows, 10 Columns + 0xB8, ///< 6 Non-Monolithic DRAM Device, 4 die, 4 Channels per package, Signal Loading Matrix 1 + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x05, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200) + 0xFF, ///< 19 tCKAVGmax = 32.002 ns + 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16 + 0x00, ///< 22 CAS Latencies supported (Third Byte) : + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns + 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die) + 0x06, ///< 30 tRFCab MSB + 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die) + 0x02, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0x00, ///< 123 FTB for tAAmin = 17.5 ns + 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns + 0x00, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x20, ///< 325 Module ID: Module Serial Number + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +// LPDDR4X 200b 16Gb die, DDP, 2 channel per die, 2x8 +// Samsung K4U6E3S4AA-MGCL +// 4267, 36-39-39-90 +// 1 rank per channel, 2 SDRAMs per channel, 2x8GB = 16GB total per channel +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xDdp16Gb200bSpd[] = { + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x10, ///< 1 SPD Revision 1.0 + 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x15, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density + 0x19, ///< 5 5 15 Rows, 10 Columns + 0x94, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1 + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x05, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200) + 0xFF, ///< 19 tCKAVGmax = 32.002 ns + 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16 + 0x00, ///< 22 CAS Latencies supported (Third Byte) : + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns + 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die) + 0x06, ///< 30 tRFCab MSB + 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die) + 0x02, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0x00, ///< 123 FTB for tAAmin = 17.5 ns + 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns + 0x00, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x20, ///< 325 Module ID: Module Serial Number + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +// LPDDR4X 200b 16Gb die, 2 channel per die, 2x8 +// Micron MT53E1G32D4NQ-046 +// 3200 +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp16Gb200bSpd[] = { + 0x23, ///< 0 384 SPD bytes used, 512 total + 0x12, ///< 1 SPD Revision 1.0 + 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM + 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM) + 0x15, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density + 0x21, ///< 5 5 15 Rows, 10 Columns + 0xB1, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1 + 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC + 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved + 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported + 0x00, ///< 10 Reserved + 0x00, ///< 11 Module Nominal Voltage: Reserved + 0x0A, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel + 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC + 0x00, ///< 14 Module Thermal Sensor: none + 0x00, ///< 15 Extended Module Type: Reserved + 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load + 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps + 0x04, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200) + 0x00, ///< 19 tCKAVGmax = 32.002 ns + 0xD2, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6 + 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16 + 0x01, ///< 22 CAS Latencies supported (Third Byte) : + 0x00, ///< 23 CAS Latencies supported (Fourth Byte): + 0x87, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns + 0x40, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled + 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns + 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns + 0xC0, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die) + 0x08, ///< 30 tRFCab MSB + 0x60, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die) + 0x04, ///< 32 tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns + 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns + 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns + 0xE4, ///< 123 FTB for tAAmin = 17.5 ns + 0x00, ///< 124 FTB for tCKAVGmax = 32.002 ns + 0x60, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267) + 0xA1, ///< 126 CRC A + 0xAC, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Location + 0x00, ///< 323 Module Manufacturing Date Year + 0x00, ///< 324 Module Manufacturing Date Week + 0x20, ///< 325 Module ID: Module Serial Number + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte + 0x00 ///< 352 DRAM Stepping + ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDdr5Spd_1Rx8[] = { + 0x30,///< 0 1024 SPD bytes total + 0x08,///< 1 SPD Revision 0.8 + 0x12,///< 2 DRAM Type: DDR5 SDRAM + 0x03,///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution + 0x04,///< 4 Monolithic SDRAM, 16 Gb SDRAM density + 0x00,///< 5 16 Rows, 10 Columns + 0x20,///< 6 x8 SDRAM I/O Width + 0x62,///< 7 8 Bank Groups, 4 Banks per Bank Group + 0x00,///< 8 Secondary SDRAM Density and Package + 0x00,///< 9 Secondary SDRAM Addressing + 0x00,///< 10 Secondary SDRAM I/O Width + 0x00,///< 11 Secondary BankGroups and Banks per Bank Group + 0x60,///< 12 PPR Supported, One row per bank group, Soft PPR Supported + 0x00,///< 13 Commercial Temperature Grade, 0 to 85 C + 0x00,///< 14 Reserved + 0x00,///< 15 Reserved + 0x00,///< 16 SDRAM Nominal Voltage VDD: 1.1V + 0x00,///< 17 SDRAM Nominal Voltage VDDQ: 1.1V + 0x00,///< 18 SDRAM Nominal Voltage VPP: 1.8V + 0x00,///< 19 Reserved + 0xA1,///< 20 tCKAVGmin LSB + 0x01,///< 21 tCKAVGmin MSB + 0xE8,///< 22 tCKAVGmax LSB + 0x03,///< 23 tCKAVGmax MSB + 0x72,///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22 + 0x15,///< 25 CAS Latencies supported (Second Byte): 44, 40, 36 + 0x00,///< 26 CAS Latencies supported (Third Byte) : + 0x00,///< 27 CAS Latencies supported (Fourth Byte): + 0x00,///< 28 CAS Latencies supported (Fifth Byte) : + 0x00,///< 29 Reserved + 0x1E,///< 30 Minimum CAS Latency (tAAmin) LSB + 0x41,///< 31 Minimum CAS Latency (tAAmin) MSB + 0x1E,///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB + 0x41,///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB + 0x1E,///< 34 Minimum Row Precharge delay (tRPmin) LSB + 0x41,///< 35 Minimum Row Precharge delay (tRPmin) MSB + 0x00,///< 36 Minimum Active to Precharge delay (tRASmin) LSB + 0x7D,///< 37 Minimum Active to Precharge delay (tRASmin) MSB + 0x1E,///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB + 0xBE,///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB + 0x30,///< 40 Minimum Write Recovery time (tWRmin) LSB + 0x75,///< 41 Minimum Write Recovery time (tWRmin) MSB + 0x27,///< 42 Refresh Recovery Delay (tRFC1min) LSB + 0x01,///< 43 Refresh Recovery Delay (tRFC1min) MSB + 0xA0,///< 44 Refresh Recovery Delay (tRFC2min) MSB + 0x00,///< 45 Refresh Recovery Delay (tRFC2min) MSB + 0x82,///< 46 Refresh Recovery Delay (tRFCsbmin) MSB + 0x00,///< 47 Refresh Recovery Delay (tRFCsbmin) MSB + 0, 0, ///< 48 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0, 0, 0, 0, 0, 0, ///< 120 - 125 + 0x47, ///< 126 CRC Bytes 0 - 127 LSB + 0xAE, ///< 127 CRC Bytes 0 - 127 MSB + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, ///< 190 - 191 + 0x08, ///< 192 SPD Revision for Module Information: 0.8 + 0x00, ///< 193 Reserved + 0xC2, ///< 194 SPD Manufacturer ID First Byte + 0xC4, ///< 195 SPD Manufacturer ID Second Byte + 0x80, ///< 196 SPD Device Type + 0x00, ///< 197 SPD Device Revision + 0x80, ///< 198 PMIC0 Manufacturer ID First Byte + 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte + 0x80, ///< 200 PMIC0 Device Type + 0x11, ///< 201 PMIC0 Device Revision + 0, 0, 0, 0, ///< 202 - 205 PMIC1 + 0, 0, 0, 0, ///< 206 - 209 PMIC2 + 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte + 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte + 0x80, ///< 212 Thermal Sensors Device Type + 0x11, ///< 213 Thermal Sensors Device Revision + 0, 0, 0, 0, 0, 0, ///< 214 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0x0F, ///< 230 Module Nominal Height + 0x10, ///< 231 Module Nominal Thickness + 0x00, ///< 232 Reference Raw Card Used + 0x01, ///< 233 1 Row of DRAM on Module + 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel + 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel + 0, 0, 0, 0, ///< 236 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445 + 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB + 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB + 0, 0, ///< 448 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 + 0, 0, ///< 510 - 511 + 0x80, ///< 512 Module Manufacturer ID First Byte + 0xAD, ///< 513 Module Manufacturer ID Second Byte + 0x00, ///< 514 Module Manufacturing Location + 0, 0, ///< 515 - 516 Module Manufacturing Date + 0, 0, 0, 0, ///< 517 - 520 Module Serial Number + 0x54, 0x4D, 0x43, 0x41, 0x32, 0x47, 0x53, 0x36, 0x41, 0x4A, ///< 521 - 530 + 0x52, 0x38, 0x43, 0x2D, 0x45, 0x42, 0x20, 0x20, 0x20, 0x20, ///< 531 - 540 + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ///< 541 - 550 + 0x00, ///< 551 Module Revision Code + 0x80, ///< 552 DRAM Manufacturer ID First Byte + 0xAD ///< 553 DRAM Manufacturer ID Second Byte + ///< 554 - 1023 are zeroes, no need to keep them, save PEI FV size +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDdr5Spd_2Rx8[] = { + 0x30,///< 0 1024 SPD bytes total + 0x08,///< 1 SPD Revision 0.8 + 0x12,///< 2 DRAM Type: DDR5 SDRAM + 0x03,///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution + 0x04,///< 4 Monolithic SDRAM, 16 Gb SDRAM density + 0x00,///< 5 16 Rows, 10 Columns + 0x20,///< 6 x8 SDRAM I/O Width + 0x62,///< 7 8 Bank Groups, 4 Banks per Bank Group + 0x00,///< 8 Secondary SDRAM Density and Package + 0x00,///< 9 Secondary SDRAM Addressing + 0x00,///< 10 Secondary SDRAM I/O Width + 0x00,///< 11 Secondary BankGroups and Banks per Bank Group + 0x60,///< 12 PPR Supported, One row per bank group, Soft PPR Supported + 0x00,///< 13 Commercial Temperature Grade, 0 to 85 C + 0x00,///< 14 Reserved + 0x00,///< 15 Reserved + 0x00,///< 16 SDRAM Nominal Voltage VDD: 1.1V + 0x00,///< 17 SDRAM Nominal Voltage VDDQ: 1.1V + 0x00,///< 18 SDRAM Nominal Voltage VPP: 1.8V + 0x00,///< 19 Reserved + 0xA1,///< 20 tCKAVGmin LSB + 0x01,///< 21 tCKAVGmin MSB + 0xE8,///< 22 tCKAVGmax LSB + 0x03,///< 23 tCKAVGmax MSB + 0x72,///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22 + 0x15,///< 25 CAS Latencies supported (Second Byte): 44, 40, 36 + 0x00,///< 26 CAS Latencies supported (Third Byte) : + 0x00,///< 27 CAS Latencies supported (Fourth Byte): + 0x00,///< 28 CAS Latencies supported (Fifth Byte) : + 0x00,///< 29 Reserved + 0x1E,///< 30 Minimum CAS Latency (tAAmin) LSB + 0x41,///< 31 Minimum CAS Latency (tAAmin) MSB + 0x1E,///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB + 0x41,///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB + 0x1E,///< 34 Minimum Row Precharge delay (tRPmin) LSB + 0x41,///< 35 Minimum Row Precharge delay (tRPmin) MSB + 0x00,///< 36 Minimum Active to Precharge delay (tRASmin) LSB + 0x7D,///< 37 Minimum Active to Precharge delay (tRASmin) MSB + 0x1E,///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB + 0xBE,///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB + 0x30,///< 40 Minimum Write Recovery time (tWRmin) LSB + 0x75,///< 41 Minimum Write Recovery time (tWRmin) MSB + 0x27,///< 42 Refresh Recovery Delay (tRFC1min) LSB + 0x01,///< 43 Refresh Recovery Delay (tRFC1min) MSB + 0xA0,///< 44 Refresh Recovery Delay (tRFC2min) MSB + 0x00,///< 45 Refresh Recovery Delay (tRFC2min) MSB + 0x82,///< 46 Refresh Recovery Delay (tRFCsbmin) MSB + 0x00,///< 47 Refresh Recovery Delay (tRFCsbmin) MSB + 0, 0, ///< 48 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0, 0, 0, 0, 0, 0, ///< 120 - 125 + 0x47, ///< 126 CRC Bytes 0 - 127 LSB + 0xAE, ///< 127 CRC Bytes 0 - 127 MSB + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, ///< 190 - 191 + 0x08, ///< 192 SPD Revision for Module Information: 0.8 + 0x00, ///< 193 Reserved + 0xC2, ///< 194 SPD Manufacturer ID First Byte + 0xC4, ///< 195 SPD Manufacturer ID Second Byte + 0x80, ///< 196 SPD Device Type + 0x00, ///< 197 SPD Device Revision + 0x80, ///< 198 PMIC0 Manufacturer ID First Byte + 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte + 0x80, ///< 200 PMIC0 Device Type + 0x11, ///< 201 PMIC0 Device Revision + 0, 0, 0, 0, ///< 202 - 205 PMIC1 + 0, 0, 0, 0, ///< 206 - 209 PMIC2 + 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte + 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte + 0x80, ///< 212 Thermal Sensors Device Type + 0x11, ///< 213 Thermal Sensors Device Revision + 0, 0, 0, 0, 0, 0, ///< 214 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0x0F, ///< 230 Module Nominal Height + 0x10, ///< 231 Module Nominal Thickness + 0x00, ///< 232 Reference Raw Card Used + 0x01, ///< 233 1 Row of DRAM on Module + 0x08, ///< 234 Module Organization: 2 Package Ranks; symmetrical rank mix + 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel + 0, 0, 0, 0, ///< 236 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445 + 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB + 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB + 0, 0, ///< 448 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 + 0, 0, ///< 510 - 511 + 0x80, ///< 512 Module Manufacturer ID First Byte + 0xAD, ///< 513 Module Manufacturer ID Second Byte + 0x00, ///< 514 Module Manufacturing Location + 0, 0, ///< 515 - 516 Module Manufacturing Date + 0, 0, 0, 0, ///< 517 - 520 Module Serial Number + 0x54, 0x4D, 0x43, 0x41, 0x32, 0x47, 0x53, 0x36, 0x41, 0x4A, ///< 521 - 530 + 0x52, 0x38, 0x43, 0x2D, 0x45, 0x42, 0x20, 0x20, 0x20, 0x20, ///< 531 - 540 + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ///< 541 - 550 + 0x00, ///< 551 Module Revision Code + 0x80, ///< 552 DRAM Manufacturer ID First Byte + 0xAD ///< 553 DRAM Manufacturer ID Second Byte + ///< 554 - 1023 are zeroes, no need to keep them, save PEI FV size +}; diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c new file mode 100644 index 0000000000..eb6e0a0f4b --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c @@ -0,0 +1,89 @@ +/** @file + Helper Library for PEI Graphics PEIM + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Library/PeiGetFvInfoLib.h> +#include <Ppi/FirmwareVolume.h> +#include <Pi/PiPeiCis.h> +#include <Core/Pei/PeiMain.h> +#include <Library/PeiServicesLib.h> +#include <Library/HobLib.h> + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section from FV + @retval EFI_NOT_FOUND File not found +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ) +{ + EFI_STATUS Status; + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; + EFI_FV_FILE_INFO FvFileInfo; + PEI_CORE_FV_HANDLE *CoreFvHandle; + EFI_PEI_FILE_HANDLE FileHandle; + EFI_GUID *FileGuid; + EFI_COMMON_SECTION_HEADER *Section; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *HobData; + + Status = PeiServicesLocatePpi( + &gEfiFirmwareFileSystem2Guid, + 0, + NULL, + (VOID **)&FvPpi + ); + ASSERT_EFI_ERROR(Status); + + GuidHob = GetFirstGuidHob (&gPlatformInitFvLocationGuid); + if (GuidHob != NULL) { + HobData = *(VOID **)GET_GUID_HOB_DATA(GuidHob); + CoreFvHandle = (PEI_CORE_FV_HANDLE *) HobData; + + // + // File typically resides in current FV or previous FV, so searching both of them. + // + Status = FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHandle, &FileHandle); + + if (!EFI_ERROR(Status) && FileHandle != NULL) { + + DEBUG((DEBUG_INFO, "Find SectionByType \n")); + + Status = FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, FileHandle, (VOID **)&FileGuid); + if (!EFI_ERROR(Status)) { + + DEBUG((DEBUG_INFO, "GetFileInfo \n")); + + Status = FvPpi->GetFileInfo(FvPpi, FileHandle, &FvFileInfo); + Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; + + if (IS_SECTION2(Section)) { + ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF); + *Size = SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER2); + *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2)); + } else { + *Size = SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER); + *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER)); + } + return EFI_SUCCESS; + } + } + } else { + DEBUG ((DEBUG_INFO, "Hob not found\n")); + } + return EFI_NOT_FOUND; +} \ No newline at end of file diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf new file mode 100644 index 0000000000..1701fb15fe --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf @@ -0,0 +1,34 @@ +### @file +# Component description file for PeiGetFvInfo library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiGetFvInfoLib + FILE_GUID = C2584BE4-2CCD-418C-9205-A2031CE75861 + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + LIBRARY_CLASS = PeiGetFvInfoLib + +[LibraryClasses] + BaseMemoryLib + BaseLib + DebugLib + DebugPrintErrorLevelLib + HobLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiGetFvInfoLib.c + +[Guids] + gPlatformInitFvLocationGuid ## CONSUMES diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c new file mode 100644 index 0000000000..fa6dc70e6b --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c @@ -0,0 +1,372 @@ +/** @file + + Source code file for the Report Firmware Volume (FV) library + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Base.h> +#include <PiPei.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/PeiServicesLib.h> +#include <Library/ReportFvLib.h> +#include <Guid/FirmwareFileSystem2.h> +#include <Ppi/FirmwareVolumeInfo.h> +#include <Ppi/ReadOnlyVariable2.h> +#include <Library/PcdLib.h> +#include <Pi/PiStatusCode.h> +#include <Library/MtrrLib.h> +#include <Library/ReportStatusCodeLib.h> + +EFI_STATUS +EFIAPI +InstallFvExtendedPostMemoryCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +EFI_STATUS +EFIAPI +InstallFvExtendedAdvancedCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +/** + Notify list for FV installation to the memory for Extended BIOS Region. + Each entry of the notify list may need to be registered based on a boot path. + Make sure what FV is installed by each callback and notify them per needs. +**/ +static EFI_PEI_NOTIFY_DESCRIPTOR mExtendedBiosDecodeReadyNotifyList [] = { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gExtendedBiosDecodeReadyPpiGuid, + InstallFvExtendedPostMemoryCallback + }, + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gExtendedBiosDecodeReadyPpiGuid, + InstallFvExtendedAdvancedCallback + }, +}; + +VOID +PrintFvHeaderInfo ( + EFI_FIRMWARE_VOLUME_HEADER *FvHeader + ); + +VOID +ReportPreMemFv ( + VOID + ) +{ + /* + Note : FSP FVs except FSP-T FV are installed in IntelFsp2Wrapper Pkg or FspPkg in Dispatch mode. + */ + if (FixedPcdGetBool (PcdFspWrapperBootMode)) { + DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvFspTBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspTBase), + PcdGet32 (PcdFlashFvFspTSize), + NULL, + NULL, + 0 + ); + } + + + DEBUG ((DEBUG_INFO, "Install FlashFvFirmwareBinaries - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvFirmwareBinariesBase), PcdGet32 (PcdFlashFvFirmwareBinariesSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvFirmwareBinariesBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFirmwareBinariesBase), + PcdGet32 (PcdFlashFvFirmwareBinariesSize), + NULL, + NULL, + 0 + ); +} + +/** + FvCnvUncompact section dependency PPI +**/ +static EFI_PEI_PPI_DESCRIPTOR mFvCnvDispatchFlagPpi = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiFvCnvDispatchFlagPpiGuid, + NULL +}; + +/** + This function call checks if this is after capsule update by BootStateAfterCapsule variable. + The variable is set to TRUE at the end of capsule update process. + The boot paths always require all FVs to be installed + so UEFI global boot option variables are initialized. + + @retval TRUE This is the first boot after capsule update. + @retval FALSE This is NOT the first boot after capsule update. +**/ +BOOLEAN +IsAfterCapsule ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; + BOOLEAN BootStateAfterCapsule; + BOOLEAN IsAfterCapsule; + BootStateAfterCapsule = FALSE; + IsAfterCapsule = FALSE; + + Status = PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **)&VariablePpi + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "IsAfterCapsule : Read Only Variable PPI is not found.\n")); + ASSERT_EFI_ERROR (Status); + return FALSE; + } + + + return IsAfterCapsule; +} + +/** + This function call installs section dependency PPIs for the child FVs in Optional FV. + + @param[out] *Installed Return TRUE if section dependencies in Optional FV are installed. + Return FALSE when none of section dependencies in Optional FV are installed. + + @retval EFI_SUCCESS Section dependency installation completes successfully. + @retval Others Section dependency installation fails to complete. +**/ +EFI_STATUS +InstallOptionalFvDependency ( + OUT BOOLEAN *Installed + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + *Installed = FALSE; + +#if FixedPcdGet8(PcdFspModeSelection) == 0 // #if Dispatch Mode + if (IsAfterCapsule ()) { +#endif + DEBUG ((DEBUG_INFO, "InstallOptionalFvDependency : Installing FvCnvUncompact dependency.\n")); + Status = PeiServicesInstallPpi (&mFvCnvDispatchFlagPpi); + *Installed = TRUE; + ASSERT_EFI_ERROR (Status); +#if FixedPcdGet8(PcdFspModeSelection) == 0 // #if Dispatch Mode + } +#endif + return Status; +} +VOID +ReportPostMemFv ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + EFI_HOB_GUID_TYPE *GuidHob; + BOOLEAN IsOptFvDependencyInstalled; + IsOptFvDependencyInstalled = FALSE; + + Status = PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + /* + Note : FSP FVs except FSP-T FV are installed in IntelFsp2WrapperPkg or FspPkg. + */ + + /// + /// Build HOB for DXE + /// + if (BootMode == BOOT_IN_RECOVERY_MODE) { + /// + /// Prepare the recovery service + /// + } else { + GuidHob = GetFirstGuidHob (&gBiosInfoRecoveryGuid); + if (GuidHob == NULL) { + DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase), + PcdGet32 (PcdFlashFvSecuritySize), + NULL, + NULL, + 0 + ); + if (BootMode != BOOT_ON_S3_RESUME) { + DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase), + PcdGet32 (PcdFlashFvAdvancedSize), + NULL, + NULL, + 0 + ); + DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase), + PcdGet32 (PcdFlashFvUefiBootSize), + NULL, + NULL, + 0 + ); + DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase), + PcdGet32 (PcdFlashFvOsBootSize), + NULL, + NULL, + 0 + ); + Status = InstallOptionalFvDependency (&IsOptFvDependencyInstalled); + if (!EFI_ERROR (Status) && IsOptFvDependencyInstalled) { + DEBUG ((DEBUG_INFO, "Install FlashFvOptional - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvOptionalBase), PcdGet32 (PcdFlashFvOptionalSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvOptionalBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvOptionalBase), + PcdGet32 (PcdFlashFvOptionalSize), + NULL, + NULL, + 0 + ); + } + } + Status = PeiServicesNotifyPpi (&mExtendedBiosDecodeReadyNotifyList [1]); + ASSERT_EFI_ERROR (Status); + } + DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase), + PcdGet32 (PcdFlashFvPostMemorySize), + NULL, + NULL, + 0 + ); + + Status = PeiServicesNotifyPpi (&mExtendedBiosDecodeReadyNotifyList [0]); + ASSERT_EFI_ERROR (Status); + + if (BootMode != BOOT_ON_S3_RESUME) { + BuildFvHob ( + (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase), + (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize) + ); + DEBUG ((DEBUG_INFO, "Build FlashFvMicrocode Hob - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvMicrocodeBase), PcdGet32 (PcdFlashFvMicrocodeSize))); + + } + } + + // + // Report resource HOB for flash FV + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE), + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize) + ); + BuildMemoryAllocationHob ( + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + EfiMemoryMappedIO + ); +} + + +/** + Callback on Extended BIOS Decode Ready Ppi so Extended PostMemory FV is installed to the memory + for Extended BIOS Region. The callback is called regardless of Extended BIOS Region support + in platform code. + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] NotifyDescriptor The notification structure this PEIM registered on install. + @param[in] Ppi The gExtendedBiosDecodeReady PPI. Not used. + + @retval EFI_SUCCESS Always returns EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +InstallFvExtendedPostMemoryCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + DEBUG ((DEBUG_INFO, "Extended BIOS Region is not supported by the image. No FV installed here\n")); + return EFI_SUCCESS; +} + + +/** + Callback on Extended BIOS Decode Ready Ppi so Extended Advanced FV is installed to the memory + for Extended BIOS Region. The callback is called regardless of Extended BIOS Region support in + platform code. Extended Advanced FV contains DXE phase drivers only and may want to be skipped + on S3 path for responsiveness. + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] NotifyDescriptor The notification structure this PEIM registered on install. + @param[in] Ppi The gExtendedBiosDecodeReady PPI. Not used. + + @retval EFI_SUCCESS Always returns EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +InstallFvExtendedAdvancedCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + DEBUG ((DEBUG_INFO, "Extended BIOS Region is not supported by the image. No FV installed here\n")); + return EFI_SUCCESS; +} + + +/** + Debug support function to output detailed information on a firmware volume being installed. + Setting DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask lets the function to be + included in a module. Refer to DEBUG_CODE macro. + + @param[in] FvHeader Pointer to firmware volume header +**/ +VOID +PrintFvHeaderInfo ( + EFI_FIRMWARE_VOLUME_HEADER *FvHeader + ) +{ + DEBUG_CODE ( + EFI_FIRMWARE_VOLUME_EXT_HEADER *FvExtHeader; + EFI_FFS_FILE_HEADER *FfsHeader; + + DEBUG ((DEBUG_INFO, "[ FV @ 0x%x ] \n", FvHeader)); + DEBUG ((DEBUG_INFO, " FV File System : %g \n", &FvHeader->FileSystemGuid)); + if (FvHeader->ExtHeaderOffset != 0) { + FvExtHeader = (EFI_FIRMWARE_VOLUME_EXT_HEADER *) ((UINT8 *) FvHeader + FvHeader->ExtHeaderOffset); + FfsHeader = (EFI_FFS_FILE_HEADER *) ((UINT8 *) FvExtHeader + FvExtHeader->ExtHeaderSize); + FfsHeader = (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (FfsHeader, 8); + DEBUG ((DEBUG_INFO, " FV GUID : %g \n", &FvExtHeader->FvName)); + DEBUG ((DEBUG_INFO, " File GUID : %g \n", &FfsHeader->Name)); + } + ); +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf new file mode 100644 index 0000000000..9e0035d445 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf @@ -0,0 +1,78 @@ +## @file +# Component information file for the PEI Report Firmware Volume (FV) library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiReportFvLib + FILE_GUID = 44328FA5-E4DD-4A15-ABDF-C6584AC363D9 + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + LIBRARY_CLASS = ReportFvLib + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + PeiServicesLib + PcdLib + MtrrLib + ReportStatusCodeLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + + +[Sources] + PeiReportFvLib.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gPeiFvCnvDispatchFlagPpiGuid ## PRODUCES + gExtendedBiosDecodeReadyPpiGuid ## CONSUMES + +[Guids] + gBiosInfoRecoveryGuid + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize ## CONSUMES + + [FixedPcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..ea2f464b99 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf @@ -0,0 +1,52 @@ +### @file +# SMM Library instance of Spi Flash Common Library Class +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmSpiFlashCommonLib + FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47 + VERSION_STRING = 1.0 + MODULE_TYPE = DXE_SMM_DRIVER + LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER + CONSTRUCTOR = SmmSpiFlashCommonLibConstructor +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[LibraryClasses] + IoLib + MemoryAllocationLib + BaseLib + UefiLib + SmmServicesTableLib + BaseMemoryLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[Pcd] + gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionSizeInUse ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionOffset ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdExtendedBiosRegionSupport ## CONSUMES + +[Sources] + SpiFlashCommonSmmLib.c + SpiFlashCommon.c + +[Protocols] + gPchSmmSpiProtocolGuid ## CONSUMES + +[Depex.X64.DXE_SMM_DRIVER] + gPchSmmSpiProtocolGuid diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..3f7c52ac73 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c @@ -0,0 +1,215 @@ +/** @file + Wrap EFI_SPI_PROTOCOL to provide some library level interfaces + for module use. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include <Library/SpiFlashCommon.h> +#include <Library/IoLib.h> + +PCH_SPI_PROTOCOL *mSpiProtocol; + +// +// Variables for boottime and runtime usage. +// +UINTN mBiosAreaBaseAddress = 0; +UINTN mBiosSize = 0; +UINTN mBiosOffset = 0; + +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + return Status; +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + ASSERT ((NumBytes != NULL) && (Buffer != NULL)); + if ((NumBytes == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // This function is implemented specifically for those platforms + // at which the SPI device is memory mapped for read. So this + // function just do a memory copy for Spi Flash Read. + // + CopyMem (Buffer, (VOID *) Address, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the write. + @param[in,out] NumBytes On input, the number of bytes to write. On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header exceeds the + size ofBIOS Guard script buffer + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes != NULL) && (Buffer != NULL)); + if ((NumBytes == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >= mBiosAreaBaseAddress); + if (Address < mBiosAreaBaseAddress) { + return EFI_INVALID_PARAMETER; + } + + Offset = Address - mBiosAreaBaseAddress; + + ASSERT ((*NumBytes + Offset) <= mBiosSize); + if ((*NumBytes + Offset) > mBiosSize) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_SUCCESS; + RemainingBytes = *NumBytes; + + while (RemainingBytes > 0) { + if (RemainingBytes > SECTOR_SIZE_4KB) { + Length = SECTOR_SIZE_4KB; + } else { + Length = RemainingBytes; + } + Status = mSpiProtocol->FlashWrite ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + Length, + Buffer + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -= Length; + Offset += Length; + Buffer += Length; + } + + // + // Actual number of bytes written + // + *NumBytes -= RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block to be erased. + This library assume that caller garantee that the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + @retval EFI_INVALID_PARAMETER Invalid parameter. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes != NULL); + if (NumBytes == NULL) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >= mBiosAreaBaseAddress); + if (Address < mBiosAreaBaseAddress) { + return EFI_INVALID_PARAMETER; + } + + Offset = Address - mBiosAreaBaseAddress; + + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0); + if ((*NumBytes % SECTOR_SIZE_4KB) != 0) { + return EFI_INVALID_PARAMETER; + } + + ASSERT ((*NumBytes + Offset) <= mBiosSize); + if ((*NumBytes + Offset) > mBiosSize) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_SUCCESS; + RemainingBytes = *NumBytes; + + Status = mSpiProtocol->FlashErase ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + (UINT32) RemainingBytes + ); + return Status; +} + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..7d74162d43 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c @@ -0,0 +1,64 @@ +/** @file + SMM Library instance of SPI Flash Common Library Class + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include <Library/SpiFlashCommon.h> +#include <Library/SmmServicesTableLib.h> + +extern PCH_SPI_PROTOCOL *mSpiProtocol; + +extern UINTN mBiosAreaBaseAddress; +extern UINTN mBiosSize; +extern UINTN mBiosOffset; + +/** + The library constructuor. + + The function does the necessary initialization work for this library + instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error code details. +**/ +EFI_STATUS +EFIAPI +SmmSpiFlashCommonLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 BaseAddr; + UINT32 RegionSize; + +#if FixedPcdGetBool(PcdExtendedBiosRegionSupport) == 0 + mBiosAreaBaseAddress = (UINTN)PcdGet32 (PcdBiosAreaBaseAddress); + mBiosSize = (UINTN)PcdGet32 (PcdBiosSize); +#else + mBiosAreaBaseAddress = (UINTN) PcdGet32 (PcdBiosAreaBaseAddress) + (UINTN) PcdGet32 (PcdFlashExtendRegionOffset); + mBiosSize = 0x1000000 + (UINTN) PcdGet32 (PcdFlashExtendRegionSizeInUse); +#endif + // + // Locate the SMM SPI protocol. + // + Status = gSmst->SmmLocateProtocol ( + &gPchSmmSpiProtocolGuid, + NULL, + (VOID **) &mSpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr, &RegionSize); + mBiosOffset = BaseAddr; + + return Status; +} -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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