Create the AlderlakeOpenBoardPkg to provide board support code. The package may support Alderlake boards. The package serves as a board support package in the EDK II Minimum Platform design.
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> Cc: Isaac Oram <isaac.w.o...@intel.com> Cc: Rosen Chuang <rosen.chu...@intel.com> Signed-off-by: Saloni Kasbekar <saloni.kasbe...@intel.com> --- .../Include/Library/BoardConfigLib.h | 157 ++++ .../Include/Library/DxeAcpiGnvsInitLib.h | 26 + .../Include/Library/PeiGetFvInfoLib.h | 29 + .../Include/Library/PeiPolicyBoardConfigLib.h | 108 +++ .../Include/Library/SpiFlashCommon.h | 99 +++ .../AlderlakeOpenBoardPkg/Include/Platform.h | 24 + .../Include/PlatformBoardConfig.h | 130 +++ .../Include/PlatformBoardId.h | 30 + .../Include/PlatformBoardType.h | 15 + .../Include/PlatformGpioConfig.h | 18 + .../Include/PlatformNvsAreaDef.h | 751 ++++++++++++++++++ .../Include/PlatformPostCode.h | 39 + .../Include/PolicyUpdateMacro.h | 48 ++ .../Include/Protocol/PlatformNvsArea.h | 36 + .../AlderlakeOpenBoardPkg/OpenBoardPkg.dec | 605 ++++++++++++++ 15 files changed, 2115 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h new file mode 100644 index 0000000000..e782028bed --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h @@ -0,0 +1,157 @@ +/** @file + Function prototype of BoardConfigLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BOARD_CONFIG_LIB_H_ +#define _BOARD_CONFIG_LIB_H_ + +#include <Library/GpioLib.h> +#include <PlatformBoardConfig.h> + +#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field)) + +#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE)) + +// +// @todo Define BOARD_CONFIG +// +#define BOARD_CONFIG PLATFORM_INFO + +#define PRE_MEM 0 +#define POST_MEM 1 +#define EARLY_PRE_MEM 2 + +/** + Procedure to detect current board HW configuration. + +**/ +VOID +EFIAPI +GetBoardConfig ( + VOID + ); + + +/** + Count the number of GPIO settings in the Table. + + @param[in] GpioTable The pointer of GPIO config table + @param[out] GpioCount The number of GPIO config entries +**/ +VOID +GetGpioTableSize ( + GPIO_INIT_CONFIG *GpioTable, + OUT UINT16 *GpioCount + ); + +/** + Configure GPIO Table setting to PcdBoardGpioTablePreMem && PcdBoardGpioTable + + @param[in] GpioTable The pointer of GPIO config table + @param[in] IsPostMem Is call from PostMem/PreMem + True - PostMem, False - PreMem +**/ +VOID +ConfigureGpioTabletoPCD( + IN GPIO_INIT_CONFIG *GpioTable, + IN UINT16 IsPostMem + ); + +/** + Configure GPIO pads in PEI phase. + + @param[in] GpioTable Pointer to Gpio table +**/ +VOID +GpioInit ( + IN GPIO_INIT_CONFIG *GpioTable + ); + +/** + Check if given rootport has device connected and enable wake capability + + @param[in] RpNum An unsigned integer represent the root port number. + + @retval TRUE if endpoint was connected + @retval FALSE if no endpoint was detected +**/ +BOOLEAN +IsPcieEndPointPresent ( + IN UINT8 RpNum + ); + +// LPDDR4 200b 8Gb die, DDP, 2 channels per die, x16 +// Samsung K4F6E304Hx-MGCJ +// or Hynix H9HCNNNBUUxLHR-NMx +// or Micron MT53B512M32D2NP-053 +// 3733, 32-34-34-79 +// 2 ranks per channel, 2 SDRAMs per channel, 2x2x8Gb = 4GB total per channel +extern const UINT8 mLpddr4Ddp8Gb200bSpd; + +// LPDDR4X 432b 16Gb die, QDP 2x16 +// Samsung K3UH7H70MM-JGCJ +// 3733, 32-34-34-79 +// 2 ranks per channel, 1 SDRAMs per rank, 4x16Gb = 8GB total per channel +extern const UINT8 mLpddr4xQdp16Gb432bSpd; + +// LPDDR4X 556b 8Gb die, ODP, 1 channel per die, x16 +// Micron MT53D1G64D8SQ-046 +// 4266 +// 2 ranks per channel, 2 SDRAMs per channel, 2x4x8Gb = 8GB total per channel +extern const UINT8 mLpddr4xOdp8Gb556bSpd; + +// LPDDR4X 556b 4Gb die, QDP, 1 channel per die, x16 +// Micron MT53D512M64D4RQ-046 WT:E +// 4266 +// 2 ranks per channel, 2 SDRAMs per channel, 2x4x8Gb = 4GB total per channel +extern const UINT8 mLpddr4xQdp4Gb556bSpd; + +extern const UINT8 mLpddr4Ddp16Gb200b1rSpd; + +// LPDDR5 496b 12Gb die, QDP 1x16 +// Samsung K3LK2K20BM-BGCN +// 5500, ??-??-??-?? +// 16 Banks, 4 bank groups, 12Gb SDRAM density +// 16 Row bits, 10 Column bits +// Non-Monolithic DRAM Device, 4 dies, 4 Channels per die, +extern const UINT8 mLpddr5xQdp12Gb496bSpd; + +// LPDDR4X 200b 16Gb die, DDP, 2 channel per die, 2x8 +// Samsung K4U6E3S4AA-MGCL +// 4267, 36-39-39-90 +// 1 rank per channel, 2 SDRAMs per channel, 2x8GB = 16GB total per channel +extern const UINT8 mLpddr4xDdp16Gb200bSpd; + +// LPDDR4X 200b 16Gb die, 2 channel per die, 2x8 +// Micron MT53E1G32D4NQ-046 +// 3200 +extern const UINT8 mLpddr4xQdp16Gb200bSpd; + +// LPDDR4X 200b 8Gb die, 4 die, 2 Channels per package +// Micron MT53E1G32D4NQ-046 +// 4267 +extern const UINT8 mLpddr4xQdp8Gb200b2r4267Spd; + +extern const UINT8 mDdr5Spd_1Rx8[]; +extern const UINT8 mDdr5Spd_2Rx8[]; + +// Default USB2 OC mapping +extern USB_OC_MAP_TABLE mUsb2OverCurrentMappingTable; +// Default USB3 OC mapping +extern USB_OC_MAP_TABLE mUsb3OverCurrentMappingTable; + +/** + Update Cpu Xhci Port Enable Map PCD from SaSetup data. + +**/ +VOID +EFIAPI +TcssUpdateCpuXhciPortEnableMapPcd ( + VOID + ); + +#endif // _BOARD_CONFIG_LIB_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h new file mode 100644 index 0000000000..2695bd4eec --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h @@ -0,0 +1,26 @@ +/** @file + Acpi Gnvs Init Library header file. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Base.h> + + +/** +@brief + Global NVS initialize. + + @param[in] PlatformNvsAreaPtr - Pointer of global NVS area + + @retval EFI_SUCCESS - Allocate Global NVS completed. + @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for PlatformNvsAreaProtocol. +**/ +EFI_STATUS +EFIAPI +AcpiGnvsInit ( + IN OUT VOID **PlatformNvsAreaPtr + ); + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h new file mode 100644 index 0000000000..5ec9c47b4e --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h @@ -0,0 +1,29 @@ +/** @file + Header file for PeiGetFvInfoLib.. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_GET_FV_INFO_LIB_H_ +#define _PEI_GET_FV_INFO_LIB_H_ + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section from FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ); + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h new file mode 100644 index 0000000000..1de17dabd2 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h @@ -0,0 +1,108 @@ +/** @file + Header file for the PeiPolicyBoardConfig Library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_ +#define _PEI_POLICY_BOARD_CONFIG_LIB_H_ + + +/** + This function performs PEI CPU Pre-Memory Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfigPreMem ( + VOID + ); + +/** + This function performs PEI ME Pre-Memory Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfigPreMem ( + VOID + ); + +/** + This function performs PEI PCH Pre-Memory Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfigPreMem ( + VOID + ); + +/** + This function performs PEI SA Pre-Memory Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfigPreMem ( + VOID + ); + +/** + This function performs PEI ME Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfig ( + VOID + ); + +/** + This function performs PEI SA Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfig ( + VOID + ); + +/** + This function performs PEI TBT Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiTbtPolicyBoardConfig ( + VOID + ); + +/** + This function performs PEI SI Policy update by board configuration. + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully updated. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicyBoardConfig ( + VOID + ); + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h new file mode 100644 index 0000000000..685d2b95a3 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h @@ -0,0 +1,99 @@ +/** @file + The header file includes the common header files, defines + internal structure and functions used by SpiFlashCommonLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SPI_FLASH_COMMON_H__ +#define __SPI_FLASH_COMMON_H__ + +#include <Uefi.h> +#include <Library/BaseLib.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiDriverEntryPoint.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/Spi.h> + +#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ); + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ); + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the write. + @param[in,out] NumBytes On input, the number of bytes to write. On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ); + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block to be erased. + This library assume that caller garantee that the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ); + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h new file mode 100644 index 0000000000..f4b15520c0 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h @@ -0,0 +1,24 @@ +/** @file + This header file provides platform specific definitions used + by other modules for platform specific initialization. + This is not suitable for consumption by ASL or VRF files. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ + + +// +// Need minimum of 48MB during PEI phase for IAG and some buffer for boot. +// +#define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB +#define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB + +#define FLASH_BLOCK_SIZE 0x10000 + + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h new file mode 100644 index 0000000000..d411dfc50c --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h @@ -0,0 +1,130 @@ +/** @file + Header file for Platform Boards Configurations. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BOARD_CONFIG_H +#define _PLATFORM_BOARD_CONFIG_H + +#include <ConfigBlock.h> +#include <PchPolicyCommon.h> +#include <MemoryConfig.h> +#include <Library/GpioConfig.h> + +#define MAX_GPIO_PINS 130 +#define MAX_PRE_MEM_GPIO_PINS 60 +#define MAX_PMAX_DEVICE_STRING_LENGTH 31 + +#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1) +#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) & 0xFFF0)) + +#define BOARD_REAL_BATTERY_SUPPORTED BIT0 +#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1 + +// +// ACPI table information used to update tables thru PCD +// +#define ACPI_OEM_TABLE_ID_ADL_P_M 0x4D2D502D4C4441 //ADL-P-M + +// +// GPIO states mapping +// +#define PIN_GPIO_ACTIVE_LOW 0 +#define PIN_GPIO_ACTIVE_HIGH 1 + +//# +//# + +#pragma pack(1) + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header +} BOARD_CONFIG_BLOCK; + +typedef struct { + UINT8 ClkReqNumber : 4; + UINT8 ClkReqSupported : 1; + UINT8 DeviceResetPadActiveHigh : 1; + UINT32 DeviceResetPad; +} ROOT_PORT_CLK_INFO; + +typedef struct { + UINT8 Section; + UINT8 Pin; +} EXPANDER_GPIO_CONFIG; + +typedef enum { + BoardGpioTypePch, + BoardGpioTypeExpander, + BoardGpioTypeNotSupported = 0xFF +} BOARD_GPIO_TYPE; + +typedef struct { + UINT8 Type; + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG + union { + UINT32 Pin; + EXPANDER_GPIO_CONFIG Expander; + } u; +} BOARD_GPIO_CONFIG; + +// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC. +#define NOT_USED 0xFF +#define LAN_CLOCK 0x70 +#define PCIE_PEG 0x40 +#define PCIE_PCH 0x00 + +typedef struct { + UINT32 ClockUsage; + UINT32 ClkReqSupported; +} PCIE_CLOCK_CONFIG; + +typedef union { + UINT64 Blob; + BOARD_GPIO_CONFIG BoardGpioConfig; + ROOT_PORT_CLK_INFO Info; + PCIE_CLOCK_CONFIG PcieClock; +} PCD64_BLOB; + +// Having Max CLK config to support both ADL P and ALD S +#define PCH_MAX_PCIE_CLOCKS_SBC 18 + +//seamless board configurations +typedef struct { + UINT32 ClockUsage[PCH_MAX_PCIE_CLOCKS_SBC]; +} PCIE_CLOCKS_USAGE; + +#define SPD_DATA_SIZE 1024 + +/** + This is a helper structure that's used to updating Config Block data according to board design +**/ +#define USB_OC_MAX_PINS 16 + +typedef struct { + UINT8 Size; + UINT8 Data[USB_OC_MAX_PINS]; +} USB_OC_MAP_TABLE; + +//SBC MRC DQS +typedef struct { + UINT8 DqsMapCpu2Dram[8][2]; +} MRC_DQS; + +//SBC MRC DQ +typedef struct { + UINT8 DqMapCpu2Dram[8][2][8]; +} MRC_DQ; + +//SBC SPD DATA +typedef struct { + BOOLEAN OverrideSpd; + UINT8 SpdData[SPD_DATA_SIZE]; +} SPD_DATA; + +#pragma pack() + +#endif // _PLATFORM_BOARD_CONFIG_H diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h new file mode 100644 index 0000000000..eb72b1d9b2 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h @@ -0,0 +1,30 @@ +/** @file +Defines Platform BoardIds + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BOARD_ID_H_ +#define _PLATFORM_BOARD_ID_H_ + +#define FlavorUnknown 0x0 +#define FlavorMobile 0x1 +#define FlavorDesktop 0x2 +#define FlavorWorkstation 0x3 +#define FlavorUpServer 0x4 + +#define TypeUnknown 0x0 +#define TypeTrad 0x1 +#define TypeUltUlx 0x2 +// +// Alderlake Sku IDs +// +#define SkuIdAdlPDdr5Rvp 0x000012 +#define AdlPSkuType 2 + +// Alderlake P Board IDs +#define BoardIdAdlPDdr5Rvp 0x12 + +#endif // _PLATFORM_BOARD_ID_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h new file mode 100644 index 0000000000..1d42f8a083 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h @@ -0,0 +1,15 @@ +/** @file + BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BOARD_TYPE_H_ +#define _PLATFORM_BOARD_TYPE_H_ + +#define BoardTypeRvp 0x00 // Reference Validation Platform +#define BoardTypeMax 0x0A + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h new file mode 100644 index 0000000000..6384766917 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h @@ -0,0 +1,18 @@ +/** @file +Defines Platform GPIO Configuration Arrary + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Library/GpioLib.h> + +#ifndef _PLATFORM_GPIO_CONFIG_H_ +#define _PLATFORM_GPIO_CONFIG_H_ + +typedef struct { + GPIO_INIT_CONFIG GpioConfig[0]; +} GPIO_INIT_CONFIG_ARRAY; + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h new file mode 100644 index 0000000000..e65d3fa37c --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h @@ -0,0 +1,751 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + +#ifndef _PLATFORM_NVS_AREA_DEF_H_ +#define _PLATFORM_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + // + // Miscellaneous Dynamic Registers: + // + UINT16 OperatingSystem; ///< Offset 0 Operating System + UINT8 SmiFunction; ///< Offset 2 SMI Function Call (ASL to SMI via I/O Trap) + UINT8 SmiParameter0; ///< Offset 3 SMIF - Parameter 0 + UINT8 SmiParameter1; ///< Offset 4 SMIF - Parameter 1 + UINT8 SciFunction; ///< Offset 5 SCI Function Call (SMI to ASL via _L00) + UINT8 SciParameter0; ///< Offset 6 SCIF - Parameter 0 + UINT8 SciParameter1; ///< Offset 7 SCIF - Parameter 1 + UINT8 GlobalLock; ///< Offset 8 Global Lock Function Call (EC Communication) + UINT8 LockParameter0; ///< Offset 9 LCKF - Parameter 0 + UINT8 LockParameter1; ///< Offset 10 LCKF - Parameter 1 + UINT8 PowerState; ///< Offset 11 Power State (AC Mode = 1) + UINT8 DebugState; ///< Offset 12 Debug State + // + // Thermal Policy Registers: + // + UINT8 EnableThermalKSC; ///< Offset 13 Enable Thermal Offset for KSC + UINT8 Ac1TripPoint; ///< Offset 14 Active Trip Point 1 + UINT8 Ac0TripPoint; ///< Offset 15 Active Trip Point + UINT8 PassiveThermalTripPoint; ///< Offset 16 Passive Trip Point + UINT8 PassiveTc1Value; ///< Offset 17 Passive Trip Point TC1 Value + UINT8 PassiveTc2Value; ///< Offset 18 Passive Trip Point TC2 Value + UINT8 PassiveTspValue; ///< Offset 19 Passive Trip Point TSP Value + UINT8 CriticalThermalTripPoint; ///< Offset 20 Critical Trip Point + // + // Revision Field: + // + UINT8 Revision; ///< Offset 21 Revison of GlobalNvsArea + // + // CPU Identification Registers: + // + UINT8 ApicEnable; ///< Offset 22 APIC Enabled by SBIOS (APIC Enabled = 1) + UINT8 ThreadCount; ///< Offset 23 Number of Enabled Threads + UINT8 CurentPdcState0; ///< Offset 24 PDC Settings, Processor 0 + UINT8 CurentPdcState1; ///< Offset 25 PDC Settings, Processor 1 + UINT8 MaximumPpcState; ///< Offset 26 Maximum PPC state + UINT32 PpmFlags; ///< Offset 27 PPM Flags (Same as CFGD) + UINT8 C6C7Latency; ///< Offset 31 C6/C7 Entry/Exit latency + // + // SIO Configuration Registers: + // + UINT8 DockedSioPresent; ///< Offset 32 National SIO Present + UINT8 DockComA; ///< Offset 33 COM A Port + UINT8 DockComB; ///< Offset 34 COM B Port + UINT8 DockLpt; ///< Offset 35 LPT Port + UINT8 DockFdc; ///< Offset 36 FDC Port + UINT8 OnboardCom; ///< Offset 37 SMSC Com Port + UINT8 OnboardComCir; ///< Offset 38 SMSC Com CIR Port + UINT8 SMSC1007; ///< Offset 39 SMSC1007 SIO Present + UINT8 WPCN381U; ///< Offset 40 WPCN381U SIO Present + UINT8 SMSC1000; ///< Offset 41 SMSC1000 SIO Present + // + // Extended Mobile Access Values + // + UINT8 EmaEnable; ///< Offset 42 EMA Enable + UINT16 EmaPointer; ///< Offset 43 EMA Pointer + UINT16 EmaLength; ///< Offset 45 EMA Length + // + // MEF Registers: + // + UINT8 MefEnable; ///< Offset 47 MEF Enable + // + // PCIe Dock Status: + // + UINT8 PcieDockStatus; ///< Offset 48 PCIe Dock Status + // + // TPM Registers + // + UINT8 MorData; ///< Offset 49 Memory Overwrite Request Data + UINT8 TcgParamter; ///< Offset 50 Used for save the Mor and/or physical presence paramter + UINT32 PPResponse; ///< Offset 51 Physical Presence request operation response + UINT8 PPRequest; ///< Offset 55 Physical Presence request operation + UINT8 LastPPRequest; ///< Offset 56 Last Physical Presence request operation + // + // SATA Registers: + // + UINT8 IdeMode; ///< Offset 57 IDE Mode (Compatible\Enhanced) + // + // Board Id + // + UINT8 PlatformId; ///< Offset 58 Platform id + UINT8 BoardType; ///< Offset 59 Board Type + // + // PCIe Hot Plug + // + UINT8 PcieOSCControl; ///< Offset 60 PCIE OSC Control + UINT8 NativePCIESupport; ///< Offset 61 Native PCIE Setup Value + // + // USB Sideband Deferring Support + // + UINT8 HostAlertVector1; ///< Offset 62 USB Sideband Deferring GPE Vector (HOST_ALERT#1) + UINT8 HostAlertVector2; ///< Offset 63 USB Sideband Deferring GPE Vector (HOST_ALERT#2) + // + // Embedded Controller Availability Flag. + // + UINT8 EcAvailable; ///< Offset 64 Embedded Controller Availability Flag. + // + // Global Variables + // + UINT8 DisplaySupportFlag; ///< Offset 65 _DOS Display Support Flag. + UINT8 InterruptModeFlag; ///< Offset 66 Global IOAPIC/8259 Interrupt Mode Flag. + UINT8 CoolingTypeFlag; ///< Offset 67 Global Cooling Type Flag. + UINT8 L01Counter; ///< Offset 68 Global L01 Counter. + // + // Thermal + // + UINT32 PlatformCpuId; ///< Offset 69 CPUID Feature Information [EAX] + UINT8 TsOnDimmEnabled; ///< Offset 73 TS-on-DIMM is chosen in SETUP and present on the DIMM + // + // Board info + // + UINT8 PlatformFlavor; ///< Offset 74 Platform Flavor + UINT16 BoardRev; ///< Offset 75 Board Rev + // + // XTU 3.0 Specification + // + UINT32 XTUBaseAddress; ///< Offset 77 XTU Continous structure Base Address + UINT32 XTUSize; ///< Offset 81 XMP Size + UINT32 XMPBaseAddress; ///< Offset 85 XMP Base Address + UINT8 DDRReferenceFreq; ///< Offset 89 DDR Reference Frequency + // + // DPPM Policies + // + UINT8 EnableActivePolicy; ///< Offset 90 EnableActivePolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + UINT8 EnablePassivePolicy; ///< Offset 91 EnablePassivePolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + UINT8 EnableCriticalPolicy; ///< Offset 92 EnableCriticalPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + UINT8 EnablePIDPolicy; ///< Offset 93 EnablePIDPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + // + // Miscellaneous Intel(R) Dynamic Tuning Technology + // + UINT32 PpccStepSize; ///< Offset 94 PPCC Step Size + UINT8 Reserved0[58]; ///< Offset 98:155 + // + // Comms Hub + // + UINT8 CommsHubEnable; ///< Offset 156 Comms Hub Enable/Disable + // + // BIOS only version of Config TDP + // + UINT8 ConfigTdpBios; ///< Offset 157 enable/disable BIOS only version of Config TDP + UINT8 DockSmi; ///< Offset 158 Dock SMI number + // + // LPC SIO configuration + // + UINT16 LpcSioPort1; ///< Offset 159 SIO config port 1 + UINT16 LpcSioPort2; ///< Offset 161 SIO config port 2 + UINT16 LpcSioPmeBar; ///< Offset 163 SIO PME Base Address + UINT8 Reserved1[334]; ///< Offset 165:498 + UINT16 DPTFRsvd0; ///< Offset 499 DPTFRsvd0 + UINT8 EnablePowerBossPolicy; ///< Offset 501 EnablePowerBossPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + UINT8 EnableVSPolicy; ///< Offset 502 EnableVSPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + UINT8 EnableRFIMPolicy; ///< Offset 503 RFI Mitigation @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + UINT8 Reserved2[11]; ///< Offset 504:514 + UINT8 VirtualGpioButtonSxBitmask; ///< Offset 515 Virtual GPIO button Notify Sleep State Change + UINT8 IuerButtonEnable; ///< Offset 516 IUER Button Enable + UINT8 IuerConvertibleEnable; ///< Offset 517 IUER Convertible Enable + UINT8 IuerDockEnable; ///< Offset 518 IUER Dock Enable + UINT8 Ps2MouseEnable; ///< Offset 519 Ps2 Mouse Enable + UINT16 M0C6; ///< Offset 520 M0D3 for SPI0 + UINT16 M1C6; ///< Offset 522 M1D3 for SPI0 + UINT16 M0C7; ///< Offset 524 M0D3 for SPI1 + UINT16 M1C7; ///< Offset 526 M1D3 for SPI1 + UINT16 M0C8; ///< Offset 528 M0D3 for SPI2 + UINT16 M1C8; ///< Offset 530 M1D3 for SPI2 + UINT8 Reserved3[203]; ///< Offset 532:734 + UINT16 M0C9; ///< Offset 735 M0D3 for UART0 + UINT16 M1C9; ///< Offset 737 M1D3 for UART0 + UINT16 M0CA; ///< Offset 739 M0D3 for UART1 + UINT16 M1CA; ///< Offset 741 M1D3 for UART1 + UINT16 M0CB; ///< Offset 743 M0D3 for UART2 + UINT16 M1CB; ///< Offset 745 M1D3 for UART2 + UINT8 Reserved4[1]; ///< Offset 747:747 + // + // Driver Mode + // + UINT32 GpioIrqRoute; ///< Offset 748 GPIO IRQ + UINT8 DriverModeSensorHub; ///< Offset 752 PIRQM 28,14(GPIO) + UINT8 EnableCpuVrTempSensorDevice; ///< Offset 753 EnableCpuVrTempSensorDevice + UINT8 EnableSsdTempSensorDevice; ///< Offset 754 EnableSsdTempSensorDevice + UINT8 BCV4; ///< Offset 755 Broadcom's Bluetooth adapter's revision + UINT8 AtmelPanelFwUpdate; ///< Offset 756 Atmel panel FW update Enable/Disable + UINT8 Reserved5[21]; ///< Offset 757:777 + UINT64 LowPowerS0IdleConstraint; ///< Offset 778 PEP Constraints + // Bit[1:0] - Storage (0:None, 1:Storage Controller, 2:Raid) + // Bit[2] - En/Dis UART0 + // Bit[3] - En/Dis UART1 + // Bit[4] - En/Dis I2C0 + // Bit[5] - En/Dis I2C1 + // Bit[6] - En/Dis XHCI + // Bit[8:7] - HD Audio (includes ADSP) (0: No Constraints or 1: D0/F1 or 3:D3) + // Bit[9] - En/Dis Gfx + // Bit[10] - En/Dis CPU + // Bit[11] - En/Dis EMMC + // Bit[12] - En/Dis SDXC + // Bit[13] - En/Dis I2C2 + // Bit[14] - En/Dis I2C3 + // Bit[15] - En/Dis I2C4 + // Bit[16] - En/Dis I2C5 + // Bit[17] - En/Dis UART2 + // Bit[18] - En/Dis SPI0 + // Bit[19] - En/Dis SPI1 + // Bit[20] - En/Dis SPI2 + // Bit[21] - En/Dis IPU0 + // Bit[22] - En/Dis CSME + // Bit[23] - En/Dis LAN(GBE) + // Bit[24] - En/Dis PEG0 + // Bit[25] - En/Dis THC0 + // Bit[26] - En/Dis THC1 + // Bit[27] - Reserved + // Bit[28] - En/Dis I2C6 + // Bit[29] - En/Dis TCSS IPs/DTBT + // Bit[30] - En/Dis GNA + // Bit[31] - En/Dis VMD0 + // Bit[32] - En/Dis HECI3 + // Bit[34:33] - PCIe Storage RP(0: No Constraints or 1: D0/F1 or 3:D3) + // Bit[36:35] - Pcie Lan (0:No Constraint or 1:D0/F1 or 3:D3) + // Bit[38:37] - Pcie Wlan (0:No Constraint or 1:D0/F1 or 3:D3) + // Bit[40:39] - Pcie Gfx (0:No Constraint or 1:D0/F1 or 3:D3) + // Bit[42:41] - Pcie Other (0:No Constraint or 1:D0/F1 or 3:D3) + // Bit[43] - En/Dis DG on x8 PEG port (PEG1) + // Bit[44] - En/Dis UFS0 + // Bit[45] - En/Dis UFS1 + // Bit[46] - En/Dis I2C7 + UINT16 VRStaggeringDelay; ///< Offset 786 VR Staggering delay + UINT8 TenSecondPowerButtonEnable; ///< Offset 788 10sec Power button support + // Bit0: 10 sec P-button Enable/Disable + // Bit1: Internal Flag + // Bit2: Rotation Lock flag, 0:unlock, 1:lock + // Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop + // Bit4: Undock / Dock Flag, 0: Undock, 1: Dock + // Bit5: VBDL Flag. 0: VBDL is not called, 1: VBDL is called, Virtual Button Driver is loaded. + // Bit7-6: Reserved for future use. + // + // Generation Id(Tock/Tick) + // + UINT8 GenerationId; ///< Offset 789 Generation Id(0=Shark bay, 1=Crescent Bay) + UINT8 Reserved6[10]; ///< Offset 790:799 + UINT32 AuxPowerLimit; ///< Offset 800 Maximum aux power available for PCIe root ports + // + // Intel(R) Dynamic Tuning Technology + // + UINT8 Reserved7[3]; ///< Offset 804:806 + UINT8 EnumerateSataPortConstraints; ///< Offset 807 Set to indicate to PEP that constraints at SATA ports should be enumerated + // + // Intel(R) Dynamic Tuning Technology + // + UINT8 Reserved8[210]; ///< Offset 808:1017 + UINT8 EnableAPPolicy; ///< Offset 1018 Adaptive Performance Policy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies + // + // Intel Serial(R) IO Sensor Device Selection + // + UINT8 SDS0; ///< Offset 1019 SerialIo Devices for controller0 + UINT8 SDS1; ///< Offset 1020 SerialIo Devices for controller1 + UINT8 SDS2; ///< Offset 1021 SerialIo Devices for controller2 + UINT8 SDS3; ///< Offset 1022 SerialIo Devices for controller3 + UINT8 SDS4; ///< Offset 1023 SerialIo Devices for controller4 + UINT8 SDS5; ///< Offset 1024 SerialIo Devices for controller5 + UINT8 SDS6; ///< Offset 1025 SerialIo Devices for controller6 + UINT8 SDS7; ///< Offset 1026 SerialIo Devices for controller7 + UINT8 SDS8; ///< Offset 1027 SerialIo Devices for controller8 + UINT8 SDS9; ///< Offset 1028 SerialIo Devices for controller9 + UINT8 SDSA; ///< Offset 1029 SerialIo Devices for controller10 + UINT8 WTVX; ///< Offset 1030 WITT test devices' version + UINT8 WITX; ///< Offset 1031 WITT test devices' connection point + UINT8 GPTD; ///< Offset 1032 GPIO test devices + UINT16 GDBT; ///< Offset 1033 GPIO test devices' debounce value, + UINT8 UTKX; ///< Offset 1035 UTK test devices' connection point + UINT8 SPTD; ///< Offset 1036 SerialIo additional test devices + UINT8 Reserved9[29]; ///< Offset 1037:1065 + UINT32 TableLoadBuffer; ///< Offset 1066 Buffer for runtime ACPI Table loading + UINT8 SDM0; ///< Offset 1070 interrupt mode for controller0 devices + UINT8 SDM1; ///< Offset 1071 interrupt mode for controller1 devices + UINT8 SDM2; ///< Offset 1072 interrupt mode for controller2 devices + UINT8 SDM3; ///< Offset 1073 interrupt mode for controller3 devices + UINT8 SDM4; ///< Offset 1074 interrupt mode for controller4 devices + UINT8 SDM5; ///< Offset 1075 interrupt mode for controller5 devices + UINT8 SDM6; ///< Offset 1076 interrupt mode for controller6 devices + UINT8 SDM7; ///< Offset 1077 interrupt mode for controller7 devices + UINT8 SDM8; ///< Offset 1078 interrupt mode for controller8 devices + UINT8 SDM9; ///< Offset 1079 interrupt mode for controller9 devices + UINT8 SDMA; ///< Offset 1080 interrupt mode for controller10 devices + UINT8 SDMB; ///< Offset 1081 interrupt mode for controller11 devices + UINT8 Reserved10[1]; ///< Offset 1082:1082 + UINT8 USTP; ///< Offset 1083 use SerialIo timing parameters + UINT8 Reserved11[41]; ///< Offset 1084:1124 + // + // MipiCam specific + // + UINT8 MipiCamControlLogic0; ///< Offset 1125 + UINT8 MipiCamControlLogic1; ///< Offset 1126 + UINT8 MipiCamControlLogic2; ///< Offset 1127 + UINT8 MipiCamControlLogic3; ///< Offset 1128 + UINT8 MipiCamControlLogic4; ///< Offset 1129 + UINT8 MipiCamControlLogic5; ///< Offset 1130 + UINT8 MipiCamLink0Enabled; ///< Offset 1131 + UINT8 MipiCamLink1Enabled; ///< Offset 1132 + UINT8 MipiCamLink2Enabled; ///< Offset 1133 + UINT8 MipiCamLink3Enabled; ///< Offset 1134 + UINT8 MipiCamLink4Enabled; ///< Offset 1135 + UINT8 MipiCamLink5Enabled; ///< Offset 1136 + UINT8 MipiCamLanesClkDiv; ///< Offset 1137 MipiCamLanesClkDiv is @deprecated as the Laneclockdivision option is added and now can be set uniquely for all the links. + // Control Logic 0 options + UINT8 MipiCamCtrlLogic0_Version; ///< Offset 1138 Version of CLDB structure + UINT8 MipiCamCtrlLogic0_Type; ///< Offset 1139 Type + UINT8 MipiCamCtrlLogic0_CrdVersion; ///< Offset 1140 Version of CRD + UINT32 MipiCamCtrlLogic0_InputClock; ///< Offset 1141 Input Clock + UINT8 MipiCamCtrlLogic0_GpioPinsEnabled; ///< Offset 1145 Number of GPIO Pins enabled + UINT8 MipiCamCtrlLogic0_GpioGroupPadNumber[6]; ///< Offset 1146 GPIO Group Pad Number + UINT8 MipiCamCtrlLogic0_GpioGroupNumber[6]; ///< Offset 1152 GPIO Group Number + UINT8 MipiCamCtrlLogic0_GpioFunction[6]; ///< Offset 1158 GPIO Function + UINT8 MipiCamCtrlLogic0_GpioActiveValue[6]; ///< Offset 1164 GPIO Active Value + UINT8 MipiCamCtrlLogic0_GpioInitialValue[6]; ///< Offset 1170 GPIO Initial Value + UINT8 MipiCamCtrlLogic0_PchClockSource; ///< Offset 1176 PCH Clock source + // Control Logic 1 options + UINT8 MipiCamCtrlLogic1_Version; ///< Offset 1177 Version of CLDB structure + UINT8 MipiCamCtrlLogic1_Type; ///< Offset 1178 Type + UINT8 MipiCamCtrlLogic1_CrdVersion; ///< Offset 1179 Version of CRD + UINT32 MipiCamCtrlLogic1_InputClock; ///< Offset 1180 Input Clock + UINT8 MipiCamCtrlLogic1_GpioPinsEnabled; ///< Offset 1184 Number of GPIO Pins enabled + UINT8 MipiCamCtrlLogic1_GpioGroupPadNumber[6]; ///< Offset 1185 GPIO Group Pad Number + UINT8 MipiCamCtrlLogic1_GpioGroupNumber[6]; ///< Offset 1191 GPIO Group Number + UINT8 MipiCamCtrlLogic1_GpioFunction[6]; ///< Offset 1197 GPIO Function + UINT8 MipiCamCtrlLogic1_GpioActiveValue[6]; ///< Offset 1203 GPIO Active Value + UINT8 MipiCamCtrlLogic1_GpioInitialValue[6]; ///< Offset 1209 GPIO Initial Value + UINT8 MipiCamCtrlLogic1_PchClockSource; ///< Offset 1215 PCH Clock source + // Control Logic 2 options + UINT8 MipiCamCtrlLogic2_Version; ///< Offset 1216 Version of CLDB structure + UINT8 MipiCamCtrlLogic2_Type; ///< Offset 1217 Type + UINT8 MipiCamCtrlLogic2_CrdVersion; ///< Offset 1218 Version of CRD + UINT32 MipiCamCtrlLogic2_InputClock; ///< Offset 1219 Input Clock + UINT8 MipiCamCtrlLogic2_GpioPinsEnabled; ///< Offset 1223 Number of GPIO Pins enabled + UINT8 MipiCamCtrlLogic2_GpioGroupPadNumber[6]; ///< Offset 1224 GPIO Group Pad Number + UINT8 MipiCamCtrlLogic2_GpioGroupNumber[6]; ///< Offset 1230 GPIO Group Number + UINT8 MipiCamCtrlLogic2_GpioFunction[6]; ///< Offset 1236 GPIO Function + UINT8 MipiCamCtrlLogic2_GpioActiveValue[6]; ///< Offset 1242 GPIO Active Value + UINT8 MipiCamCtrlLogic2_GpioInitialValue[6]; ///< Offset 1248 GPIO Initial Value + UINT8 MipiCamCtrlLogic2_PchClockSource; ///< Offset 1254 PCH Clock source + // Control Logic 3 options + UINT8 MipiCamCtrlLogic3_Version; ///< Offset 1255 Version of CLDB structure + UINT8 MipiCamCtrlLogic3_Type; ///< Offset 1256 Type + UINT8 MipiCamCtrlLogic3_CrdVersion; ///< Offset 1257 Version of CRD + UINT32 MipiCamCtrlLogic3_InputClock; ///< Offset 1258 Input Clock + UINT8 MipiCamCtrlLogic3_GpioPinsEnabled; ///< Offset 1262 Number of GPIO Pins enabled + UINT8 MipiCamCtrlLogic3_GpioGroupPadNumber[6]; ///< Offset 1263 GPIO Group Pad Number + UINT8 MipiCamCtrlLogic3_GpioGroupNumber[6]; ///< Offset 1269 GPIO Group Number + UINT8 MipiCamCtrlLogic3_GpioFunction[6]; ///< Offset 1275 GPIO Function + UINT8 MipiCamCtrlLogic3_GpioActiveValue[6]; ///< Offset 1281 GPIO Active Value + UINT8 MipiCamCtrlLogic3_GpioInitialValue[6]; ///< Offset 1287 GPIO Initial Value + UINT8 MipiCamCtrlLogic3_PchClockSource; ///< Offset 1293 PCH Clock source + // Control Logic 4 options + UINT8 MipiCamCtrlLogic4_Version; ///< Offset 1294 Version of CLDB structure + UINT8 MipiCamCtrlLogic4_Type; ///< Offset 1295 Type + UINT8 MipiCamCtrlLogic4_CrdVersion; ///< Offset 1296 Version of CRD + UINT32 MipiCamCtrlLogic4_InputClock; ///< Offset 1297 Input Clock + UINT8 MipiCamCtrlLogic4_GpioPinsEnabled; ///< Offset 1301 Number of GPIO Pins enabled + UINT8 MipiCamCtrlLogic4_GpioGroupPadNumber[6]; ///< Offset 1302 GPIO Group Pad Number + UINT8 MipiCamCtrlLogic4_GpioGroupNumber[6]; ///< Offset 1308 GPIO Group Number + UINT8 MipiCamCtrlLogic4_GpioFunction[6]; ///< Offset 1314 GPIO Function + UINT8 MipiCamCtrlLogic4_GpioActiveValue[6]; ///< Offset 1320 GPIO Active Value + UINT8 MipiCamCtrlLogic4_GpioInitialValue[6]; ///< Offset 1326 GPIO Initial Value + UINT8 MipiCamCtrlLogic4_PchClockSource; ///< Offset 1332 PCH Clock source + // Control Logic 5 options + UINT8 MipiCamCtrlLogic5_Version; ///< Offset 1333 Version of CLDB structure + UINT8 MipiCamCtrlLogic5_Type; ///< Offset 1334 Type + UINT8 MipiCamCtrlLogic5_CrdVersion; ///< Offset 1335 Version of CRD + UINT32 MipiCamCtrlLogic5_InputClock; ///< Offset 1336 Input Clock + UINT8 MipiCamCtrlLogic5_GpioPinsEnabled; ///< Offset 1340 Number of GPIO Pins enabled + UINT8 MipiCamCtrlLogic5_GpioGroupPadNumber[6]; ///< Offset 1341 GPIO Group Pad Number + UINT8 MipiCamCtrlLogic5_GpioGroupNumber[6]; ///< Offset 1347 GPIO Group Number + UINT8 MipiCamCtrlLogic5_GpioFunction[6]; ///< Offset 1353 GPIO Function + UINT8 MipiCamCtrlLogic5_GpioActiveValue[6]; ///< Offset 1359 GPIO Active Value + UINT8 MipiCamCtrlLogic5_GpioInitialValue[6]; ///< Offset 1365 GPIO Initial Value + UINT8 MipiCamCtrlLogic5_PchClockSource; ///< Offset 1371 PCH Clock source + // Mipi Cam Link0 options + UINT8 MipiCamLink0SensorModel; ///< Offset 1372 Sensor Model + UINT8 MipiCamLink0DD_Version; ///< Offset 1373 Version of SSDB structure + UINT8 MipiCamLink0DD_CrdVersion; ///< Offset 1374 Version of CRD + UINT8 MipiCamLink0DD_LinkUsed; ///< Offset 1375 CSI2 Link used + UINT8 MipiCamLink0DD_LaneUsed; ///< Offset 1376 MIPI-CSI2 Data Lane + UINT8 MipiCamLink0DD_EepromType; ///< Offset 1377 EEPROM Type + UINT8 MipiCamLink0DD_VcmType; ///< Offset 1378 VCM Type + UINT8 MipiCamLink0DD_FlashSupport; ///< Offset 1379 Flash Support + UINT8 MipiCamLink0DD_Degree; ///< Offset 1380 Degree + UINT32 MipiCamLink0DD_Mclk; ///< Offset 1381 MCLK + UINT8 MipiCamLink0DD_ControlLogic; ///< Offset 1385 Control Logic + UINT8 MipiCamLink0DD_PmicPosition; ///< Offset 1386 PMIC Position + UINT8 MipiCamLink0DD_VoltageRail; ///< Offset 1387 Voltage Rail + UINT8 MipiCamLink0_FlashDriverSelection; ///< Offset 1388 Flash Driver Selection + // Mipi Cam Link1 options + UINT8 MipiCamLink1SensorModel; ///< Offset 1389 Sensor Model + UINT8 MipiCamLink1DD_Version; ///< Offset 1390 Version of SSDB structure + UINT8 MipiCamLink1DD_CrdVersion; ///< Offset 1391 Version of CRD + UINT8 MipiCamLink1DD_LinkUsed; ///< Offset 1392 CSI2 Link used + UINT8 MipiCamLink1DD_LaneUsed; ///< Offset 1393 MIPI-CSI2 Data Lane + UINT8 MipiCamLink1DD_EepromType; ///< Offset 1394 EEPROM Type + UINT8 MipiCamLink1DD_VcmType; ///< Offset 1395 VCM Type + UINT8 MipiCamLink1DD_FlashSupport; ///< Offset 1396 Flash Support + UINT8 MipiCamLink1DD_Degree; ///< Offset 1397 Degree + UINT32 MipiCamLink1DD_Mclk; ///< Offset 1398 MCLK + UINT8 MipiCamLink1DD_ControlLogic; ///< Offset 1402 Control Logic + UINT8 MipiCamLink1DD_PmicPosition; ///< Offset 1403 PMIC Position + UINT8 MipiCamLink1DD_VoltageRail; ///< Offset 1404 Voltage Rail + UINT8 MipiCamLink1_FlashDriverSelection; ///< Offset 1405 Flash Driver Selection + // Mipi Cam Link2 options + UINT8 MipiCamLink2SensorModel; ///< Offset 1406 Sensor Model + UINT8 MipiCamLink2DD_Version; ///< Offset 1407 Version of SSDB structure + UINT8 MipiCamLink2DD_CrdVersion; ///< Offset 1408 Version of CRD + UINT8 MipiCamLink2DD_LinkUsed; ///< Offset 1409 CSI2 Link used + UINT8 MipiCamLink2DD_LaneUsed; ///< Offset 1410 MIPI-CSI2 Data Lane + UINT8 MipiCamLink2DD_EepromType; ///< Offset 1411 EEPROM Type + UINT8 MipiCamLink2DD_VcmType; ///< Offset 1412 VCM Type + UINT8 MipiCamLink2DD_FlashSupport; ///< Offset 1413 Flash Support + UINT8 MipiCamLink2DD_Degree; ///< Offset 1414 Degree + UINT32 MipiCamLink2DD_Mclk; ///< Offset 1415 MCLK + UINT8 MipiCamLink2DD_ControlLogic; ///< Offset 1419 Control Logic + UINT8 MipiCamLink2DD_PmicPosition; ///< Offset 1420 PMIC Position + UINT8 MipiCamLink2DD_VoltageRail; ///< Offset 1421 Voltage Rail + UINT8 MipiCamLink2_FlashDriverSelection; ///< Offset 1422 Flash Driver Selection + // Mipi Cam Link3 options + UINT8 MipiCamLink3SensorModel; ///< Offset 1423 Sensor Model + UINT8 MipiCamLink3DD_Version; ///< Offset 1424 Version of SSDB structure + UINT8 MipiCamLink3DD_CrdVersion; ///< Offset 1425 Version of CRD + UINT8 MipiCamLink3DD_LinkUsed; ///< Offset 1426 CSI2 Link used + UINT8 MipiCamLink3DD_LaneUsed; ///< Offset 1427 MIPI-CSI2 Data Lane + UINT8 MipiCamLink3DD_EepromType; ///< Offset 1428 EEPROM Type + UINT8 MipiCamLink3DD_VcmType; ///< Offset 1429 VCM Type + UINT8 MipiCamLink3DD_FlashSupport; ///< Offset 1430 Flash Support + UINT8 MipiCamLink3DD_Degree; ///< Offset 1431 Degree + UINT32 MipiCamLink3DD_Mclk; ///< Offset 1432 MCLK + UINT8 MipiCamLink3DD_ControlLogic; ///< Offset 1436 Control Logic + UINT8 MipiCamLink3DD_PmicPosition; ///< Offset 1437 PMIC Position + UINT8 MipiCamLink3DD_VoltageRail; ///< Offset 1438 Voltage Rail + UINT8 MipiCamLink3_FlashDriverSelection; ///< Offset 1439 Flash Driver Selection + // Mipi Cam Link4 options + UINT8 MipiCamLink4SensorModel; ///< Offset 1440 Sensor Model + UINT8 MipiCamLink4DD_Version; ///< Offset 1441 Version of SSDB structure + UINT8 MipiCamLink4DD_CrdVersion; ///< Offset 1442 Version of CRD + UINT8 MipiCamLink4DD_LinkUsed; ///< Offset 1443 CSI2 Link used + UINT8 MipiCamLink4DD_LaneUsed; ///< Offset 1444 MIPI-CSI2 Data Lane + UINT8 MipiCamLink4DD_EepromType; ///< Offset 1445 EEPROM Type + UINT8 MipiCamLink4DD_VcmType; ///< Offset 1446 VCM Type + UINT8 MipiCamLink4DD_FlashSupport; ///< Offset 1447 Flash Support + UINT8 MipiCamLink4DD_Degree; ///< Offset 1448 Degree + UINT32 MipiCamLink4DD_Mclk; ///< Offset 1449 MCLK + UINT8 MipiCamLink4DD_ControlLogic; ///< Offset 1453 Control Logic + UINT8 MipiCamLink4DD_PmicPosition; ///< Offset 1454 PMIC Position + UINT8 MipiCamLink4DD_VoltageRail; ///< Offset 1455 Voltage Rail + UINT8 MipiCamLink4_FlashDriverSelection; ///< Offset 1456 Flash Driver Selection + // Mipi Cam Link5 options + UINT8 MipiCamLink5SensorModel; ///< Offset 1457 Sensor Model + UINT8 MipiCamLink5DD_Version; ///< Offset 1458 Version of SSDB structure + UINT8 MipiCamLink5DD_CrdVersion; ///< Offset 1459 Version of CRD + UINT8 MipiCamLink5DD_LinkUsed; ///< Offset 1460 CSI2 Link used + UINT8 MipiCamLink5DD_LaneUsed; ///< Offset 1461 MIPI-CSI2 Data Lane + UINT8 MipiCamLink5DD_EepromType; ///< Offset 1462 EEPROM Type + UINT8 MipiCamLink5DD_VcmType; ///< Offset 1463 VCM Type + UINT8 MipiCamLink5DD_FlashSupport; ///< Offset 1464 Flash Support + UINT8 MipiCamLink5DD_Degree; ///< Offset 1465 Degree + UINT32 MipiCamLink5DD_Mclk; ///< Offset 1466 MCLK + UINT8 MipiCamLink5DD_ControlLogic; ///< Offset 1470 Control Logic + UINT8 MipiCamLink5DD_PmicPosition; ///< Offset 1471 PMIC Position + UINT8 MipiCamLink5DD_VoltageRail; ///< Offset 1472 Voltage Rail + UINT8 MipiCamLink5_FlashDriverSelection; ///< Offset 1473 Flash Driver Selection + UINT8 MipiCamFlash0Model; ///< Offset 1474 Flash Driver Model + UINT8 MipiCamFlash0Mode; ///< Offset 1475 Flash Mode Selection + UINT8 MipiCamFlash0ModuleName[16]; ///< Offset 1476 Flash Module Name ASCII character 0 + ///< Offset 1491 Flash Module Name ASCII character 15 + UINT8 MipiCamFlash0GpioGroupPadNumber; ///< Offset 1492 GPIO Group Pad Number + UINT16 MipiCamFlash0GpioGroupNumber; ///< Offset 1493 GPIO Group Number + UINT8 MipiCamFlash0GpioActiveValue; ///< Offset 1495 GPIO Active Value + UINT8 MipiCamFlash0GpioInitialValue; ///< Offset 1496 GPIO Initial Value + UINT8 MipiCamFlash0OperatingMode; ///< Offset 1497 Flash Driver Operating Mode + UINT8 MipiCamFlash1Model; ///< Offset 1498 Flash Driver Model + UINT8 MipiCamFlash1Mode; ///< Offset 1499 Flash Mode Selection + UINT8 MipiCamFlash1ModuleName[16]; ///< Offset 1500 Flash Module Name ASCII character 0 + ///< Offset 1515 Flash Module Name ASCII character 15 + UINT8 MipiCamFlash1GpioGroupPadNumber; ///< Offset 1516 GPIO Group Pad Number + UINT16 MipiCamFlash1GpioGroupNumber; ///< Offset 1517 GPIO Group Number + UINT8 MipiCamFlash1GpioActiveValue; ///< Offset 1519 GPIO Active Value + UINT8 MipiCamFlash1GpioInitialValue; ///< Offset 1520 GPIO Initial Value + UINT8 MipiCamFlash1OperatingMode; ///< Offset 1521 Flash Driver Operating Mode + UINT8 MipiCamFlash2Model; ///< Offset 1522 Flash Driver Model + UINT8 MipiCamFlash2Mode; ///< Offset 1523 Flash Mode Selection + UINT8 MipiCamFlash2ModuleName[16]; ///< Offset 1524 Flash Module Name ASCII character 0 + ///< Offset 1539 Flash Module Name ASCII character 15 + UINT8 MipiCamFlash2GpioGroupPadNumber; ///< Offset 1540 GPIO Group Pad Number + UINT16 MipiCamFlash2GpioGroupNumber; ///< Offset 1541 GPIO Group Number + UINT8 MipiCamFlash2GpioActiveValue; ///< Offset 1543 GPIO Active Value + UINT8 MipiCamFlash2GpioInitialValue; ///< Offset 1544 GPIO Initial Value + UINT8 MipiCamFlash2OperatingMode; ///< Offset 1545 Flash Driver Operating Mode + UINT8 MipiCamFlash3Model; ///< Offset 1546 Flash Driver Model + UINT8 MipiCamFlash3Mode; ///< Offset 1547 Flash Mode Selection + UINT8 MipiCamFlash3ModuleName[16]; ///< Offset 1548 Flash Module Name ASCII character 0 + ///< Offset 1563 Flash Module Name ASCII character 15 + UINT8 MipiCamFlash3GpioGroupPadNumber; ///< Offset 1564 GPIO Group Pad Number + UINT16 MipiCamFlash3GpioGroupNumber; ///< Offset 1565 GPIO Group Number + UINT8 MipiCamFlash3GpioActiveValue; ///< Offset 1567 GPIO Active Value + UINT8 MipiCamFlash3GpioInitialValue; ///< Offset 1568 GPIO Initial Value + UINT8 MipiCamFlash3OperatingMode; ///< Offset 1569 Flash Driver Operating Mode + UINT8 MipiCamFlash4Model; ///< Offset 1570 Flash Driver Model + UINT8 MipiCamFlash4Mode; ///< Offset 1571 Flash Mode Selection + UINT8 MipiCamFlash4ModuleName[16]; ///< Offset 1572 Flash Module Name ASCII character 0 + ///< Offset 1587 Flash Module Name ASCII character 15 + UINT8 MipiCamFlash4GpioGroupPadNumber; ///< Offset 1588 GPIO Group Pad Number + UINT16 MipiCamFlash4GpioGroupNumber; ///< Offset 1589 GPIO Group Number + UINT8 MipiCamFlash4GpioActiveValue; ///< Offset 1591 GPIO Active Value + UINT8 MipiCamFlash4GpioInitialValue; ///< Offset 1592 GPIO Initial Value + UINT8 MipiCamFlash4OperatingMode; ///< Offset 1593 Flash Driver Operating Mode + UINT8 MipiCamFlash5Model; ///< Offset 1594 Flash Driver Model + UINT8 MipiCamFlash5Mode; ///< Offset 1595 Flash Mode Selection + UINT8 MipiCamFlash5ModuleName[16]; ///< Offset 1596 Flash Module Name ASCII character 0 + ///< Offset 1611 Flash Module Name ASCII character 15 + UINT8 MipiCamFlash5GpioGroupPadNumber; ///< Offset 1612 GPIO Group Pad Number + UINT16 MipiCamFlash5GpioGroupNumber; ///< Offset 1613 GPIO Group Number + UINT8 MipiCamFlash5GpioActiveValue; ///< Offset 1615 GPIO Active Value + UINT8 MipiCamFlash5GpioInitialValue; ///< Offset 1616 GPIO Initial Value + UINT8 MipiCamFlash5OperatingMode; ///< Offset 1617 Flash Driver Operating Mode + UINT8 Reserved12[502]; ///< Offset 1618:2119 + // RTD3 Settings + UINT8 Reserved13[24]; ///< Offset 2120:2143 + UINT8 HidEventFilterEnable; ///< Offset 2144 HID Event Filter Driver enable + UINT8 XdciFnEnable; ///< Offset 2145 XDCI Enable/Disable status + UINT8 EnableVoltageMargining; ///< Offset 2146 Enable Voltage Margining + UINT16 DStateHSPort; ///< Offset 2147 D-State for xHCI HS port(BIT0:USB HS Port0 ~ BIT15:USB HS Port15) + UINT16 DStateSSPort; ///< Offset 2149 D-State for xHCI SS port(BIT0:USB SS Port0 ~ BIT15:USB SS Port15) + UINT8 DStateSataPort; ///< Offset 2151 D-State for SATA port(BIT0:SATA Port0 ~ BIT7:SATA Port7) + UINT8 Reserved14[154]; ///< Offset 2152:2305 + // Reserved for Groups 4 to 9, each needs 6 bytes and total 36 bytes reserved + UINT8 Reserved15[11]; ///< Offset 2306:2316 + // Reserved for Bluetooth Sar future use + UINT8 RunTimeVmControl; ///< Offset 2317 RunTime VM Control + // + //Feature Specific Data Bits + // + UINT32 HebcValue; ///< Offset 2318 HebcValue + UINT8 PcdBatteryPresent; ///< Offset 2322 Battery Present - Bit0: Real Battery is supported on this platform. Bit1: Virtual Battery is supported on this platform. + UINT8 PcdTsOnDimmTemperature; ///< Offset 2323 TS-on-DIMM temperature + UINT8 Reserved16[5]; ///< Offset 2324:2328 + UINT8 PcdRealBattery1Control; ///< Offset 2329 Real Battery 1 Control + UINT8 PcdRealBattery2Control; ///< Offset 2330 Real Battery 2 Control + UINT8 PcdNCT6776FCOM; ///< Offset 2331 NCT6776F COM + UINT8 PcdNCT6776FSIO; ///< Offset 2332 NCT6776F SIO + UINT8 PcdNCT6776FHWMON; ///< Offset 2333 NCT6776F HWMON + UINT8 PcdH8S2113SIO; ///< Offset 2334 H8S2113 SIO + UINT8 PcdZPoddConfig; ///< Offset 2335 ZPODD + UINT32 PcdSmcRuntimeSciPin; ///< Offset 2336 SMC Runtime Sci Pin + UINT8 PcdConvertableDockSupport; ///< Offset 2340 Convertable Dock Support + UINT8 PcdEcHotKeyF3Support; ///< Offset 2341 Ec Hotkey F3 Support + UINT8 PcdEcHotKeyF4Support; ///< Offset 2342 Ec Hotkey F4 Support + UINT8 PcdEcHotKeyF5Support; ///< Offset 2343 Ec Hotkey F5 Support + UINT8 PcdEcHotKeyF6Support; ///< Offset 2344 Ec Hotkey F6 Support + UINT8 PcdEcHotKeyF7Support; ///< Offset 2345 Ec Hotkey F7 Support + UINT8 PcdEcHotKeyF8Support; ///< Offset 2346 Ec Hotkey F8 Support + UINT8 PcdVirtualButtonVolumeUpSupport; ///< Offset 2347 Virtual Button Volume Up Support + UINT8 PcdVirtualButtonVolumeDownSupport; ///< Offset 2348 Virtual Button Volume Down Support + UINT8 PcdVirtualButtonHomeButtonSupport; ///< Offset 2349 Virtual Button Home Button Support + UINT8 PcdVirtualButtonRotationLockSupport; ///< Offset 2350 Virtual Button Rotation Lock Support + UINT8 PcdSlateModeSwitchSupport; ///< Offset 2351 Slate Mode Switch Support + UINT8 PcdVirtualGpioButtonSupport; ///< Offset 2352 Virtual Button Support + UINT8 PcdAcDcAutoSwitchSupport; ///< Offset 2353 Ac Dc Auto Switch Support + UINT32 PcdPmPowerButtonGpioPin; ///< Offset 2354 Pm Power Button Gpio Pin + UINT8 PcdAcpiEnableAllButtonSupport; ///< Offset 2358 Acpi Enable All Button Support + UINT8 PcdAcpiHidDriverButtonSupport; ///< Offset 2359 Acpi Hid Driver Button Support + UINT32 EcLowPowerModeGpioPin; ///< Offset 2360 EcLowPowerModeGpioPin + UINT32 EcSmiGpioPin; ///< Offset 2364 EcSmiGpioPin + // + // UCMC setup option, GPIO Pad + // + UINT8 UCMS; ///< Offset 2368 Option to select UCSI/UCMC device + UINT32 UcmcPort1Gpio; ///< Offset 2369 Gpio for UCMC Port 1 Interrupt + UINT32 UcmcPort2Gpio; ///< Offset 2373 Gpio for UCMC Port 2 Interrupt + UINT32 UcmcPort3Gpio; ///< Offset 2377 Gpio for UCMC Port 3 Interrupt + UINT32 UcmcPort4Gpio; ///< Offset 2381 Gpio for UCMC Port 4 Interrupt + UINT8 Reserved17[24]; ///< Offset 2385:2408 + UINT8 Reserved18[4]; ///< Offset 2409:2412 + UINT8 Ufp2DfpGlobalFlag; ///< Offset 2413 Upstream Facing port or Downstream Facing port Global Flag from LPC EC + UINT8 Ufp2DfpUsbPort; ///< Offset 2414 Upstream Facing port or Downstream Facing port number from LPC EC + UINT8 DbcGlobalFlag; ///< Offset 2415 Debug Mode Global Flag from LPC EC + UINT8 DbcUsbPort; ///< Offset 2416 Debug Mode USB Port Number from LPC EC + UINT32 PcieSlot1WakeGpio; ///< Offset 2417 Pcie Slot Wake Gpio pin + UINT8 PcieSlot1RpNumber; ///< Offset 2421 Pcie Slot Root Port Number + UINT32 PcieSlot2WakeGpio; ///< Offset 2422 Pcie Slot 2 Wake Gpio pin + UINT8 PcieSlot2RpNumber; ///< Offset 2426 Pcie Slot 2 Root Port Number + UINT32 PcieSlot1PowerEnableGpio; ///< Offset 2427 Pcie Slot 1 Power Enable Gpio pin + UINT8 PcieSlot1PowerEnableGpioPolarity; ///< Offset 2431 Pcie Slot 1 Power Enable Gpio pin polarity + UINT32 PcieSlot1RstGpio; ///< Offset 2432 Pcie Slot 1 Rest Gpio pin + UINT8 PcieSlot1RstGpioPolarity; ///< Offset 2436 Pcie Slot 1 Rest Gpio pin polarity + UINT32 PcieSlot2PowerEnableGpio; ///< Offset 2437 Pcie Slot 2 Power Enable Gpio pin + UINT8 PcieSlot2PowerEnableGpioPolarity; ///< Offset 2441 Pcie Slot 2 Power Enable Gpio pin polarity + UINT32 PcieSlot2RstGpio; ///< Offset 2442 Pcie Slot 2 Rest Gpio pin + UINT8 PcieSlot2RstGpioPolarity; ///< Offset 2446 Pcie Slot 2 Rest Gpio pin polarity + UINT32 SataPortPowerEnableGpio; ///< Offset 2447 Sata port Power Enable Gpio pin + UINT8 SataPortPowerEnableGpioPolarity; ///< Offset 2451 Sata port Power Enable Gpio pin polarity + UINT32 PchM2SsdPowerEnableGpio; ///< Offset 2452 Pch M.2 SSD Power Enable Gpio pin + UINT8 PchM2SsdPowerEnableGpioPolarity; ///< Offset 2456 Pch M.2 SSD Power Enable Gpio pin polarity + UINT32 PchM2SsdRstGpio; ///< Offset 2457 Pch M.2 SSD Reset Gpio pin + UINT8 PchM2SsdRstGpioPolarity; ///< Offset 2461 Pch M.2 SSD Reset Gpio pin polarity + UINT32 M2Ssd2PowerEnableGpio; ///< Offset 2462 PCIe x4 M.2 SSD Power Enable Gpio pin + UINT8 M2Ssd2PowerEnableGpioPolarity; ///< Offset 2466 PCIe x4 M.2 SSD Power Enable Gpio pin polarity + UINT32 M2Ssd2RstGpio; ///< Offset 2467 PCIe x4 M.2 SSD Reset Gpio pin + UINT8 M2Ssd2RstGpioPolarity; ///< Offset 2471 PCIe x4 M.2 SSD Reset Gpio pin polarity + UINT32 M2Ssd3PowerEnableGpio; ///< Offset 2472 PCIe x4 M.2 SSD Power Enable Gpio pin + UINT8 M2Ssd3PowerEnableGpioPolarity; ///< Offset 2476 PCIe x4 M.2 SSD Power Enable Gpio pin polarity + UINT32 M2Ssd3RstGpio; ///< Offset 2477 PCIe x4 M.2 SSD Reset Gpio pin + UINT8 M2Ssd3RstGpioPolarity; ///< Offset 2481 PCIe x4 M.2 SSD Reset Gpio pin polarity + UINT32 M2DG2PowerEnableGpio; ///< Offset 2482 PCIe x5 M.2 Discrete Graphics Power Enable Gpio Pin + UINT8 M2DG2PowerEnableGpioPolarity; ///< Offset 2486 PCIe x5 M.2 Discrete Graphics Power Enable Gpio Pin polarity + UINT32 M2DG2RstGpio; ///< Offset 2487 PCIe x5 M.2 Discrete Graphics Reset Gpio Pin + UINT8 M2DG2RstGpioPolarity; ///< Offset 2491 PCIe x5 M.2 Discrete Graphics Reset Gpio Pin Polarity + UINT32 M2DG2WakeGpioPin; ///< Offset 2492 PEG X8 DG/DG2 Wake Gpio pin + UINT8 SdevXhciRootPortNumber1; ///< Offset 2496 SDEV xHCI Root Port Number for device 1 + UINT8 SdevXhciRootPortNumber2; ///< Offset 2497 SDEV xHCI Root Port Number for device 2 + UINT8 TsnPcsEnabled; ///< Offset 2498 TSN PCS device Enable + UINT8 CpuWakeEnFlag; ///< Offset 2499 CPU_WAKE_EN value + UINT32 Dg1VramSRGpio; ///< Offset 2500 DG1 VRAM Self Refresh Gpio pin + UINT32 LpmReqRegAddr; ///< Offset 2504 Low Power Mode required register Address + UINT32 PegSlot1PwrEnableGpioNo; ///< Offset 2508 PEG slot 1 Power Enable Gpio pin + UINT8 PegSlot1PwrEnableGpioPolarity; ///< Offset 2512 PEG slot 1 Power Enable Gpio pin polarity + UINT32 PegSlot1RstGpioNo; ///< Offset 2513 PEG slot 1 Reset Gpio pin + UINT8 PegSlot1RstGpioPolarity; ///< Offset 2517 PEG slot 1 Reset Gpio pin polarity + UINT32 PegSlot1WakeGpioPin; ///< Offset 2518 PEG slot 1 Wake Gpio pin + UINT8 PegSlot1RootPort; ///< Offset 2522 PEG slot 1 Root Port + UINT32 PegSlot2PwrEnableGpioNo; ///< Offset 2523 PEG slot 2 Power Enable Gpio pin + UINT8 PegSlot2PwrEnableGpioPolarity; ///< Offset 2527 PEG slot 2 Power Enable Gpio pin polarity + UINT32 PegSlot2RstGpioNo; ///< Offset 2528 PEG slot 2 Reset Gpio pin + UINT8 PegSlot2RstGpioPolarity; ///< Offset 2532 PEG slot 2 Reset Gpio pin polarity + UINT32 PegSlot2WakeGpioPin; ///< Offset 2533 PEG slot 2 Wake Gpio pin + UINT8 PegSlot2RootPort; ///< Offset 2537 PEG slot 2 Root Port + UINT32 PcieSlot3PowerEnableGpio; ///< Offset 2538 Pcie Slot 3 Power Enable Gpio pin + UINT8 PcieSlot3PowerEnableGpioPolarity; ///< Offset 2542 Pcie Slot 3 Power Enable Gpio pin polarity + UINT32 PcieSlot3RstGpio; ///< Offset 2543 Pcie Slot 3 Rest Gpio pin + UINT8 PcieSlot3RstGpioPolarity; ///< Offset 2547 Pcie Slot 3 Rest Gpio pin polarity + UINT32 PcieSlot3WakeGpio; ///< Offset 2548 Pcie Slot 3 Wake Gpio pin + UINT8 PcieSlot3RpNumber; ///< Offset 2552 Pcie Slot 3 Root Port Number + UINT32 PchM2Ssd2PowerEnableGpio; ///< Offset 2553 Pch M.2 SSD2 Power Enable Gpio pin + UINT8 PchM2Ssd2PowerEnableGpioPolarity; ///< Offset 2557 Pch M.2 SSD2 Power Enable Gpio pin polarity + UINT32 PchM2Ssd2RstGpio; ///< Offset 2558 Pch M.2 SSD2 Reset Gpio pin + UINT8 PchM2Ssd2RstGpioPolarity; ///< Offset 2562 Pch M.2 SSD2 Reset Gpio pin polarity + UINT32 PchM2Ssd3PowerEnableGpio; ///< Offset 2563 Pch M.2 SSD3 Power Enable Gpio pin + UINT8 PchM2Ssd3PowerEnableGpioPolarity; ///< Offset 2567 Pch M.2 SSD3 Power Enable Gpio pin polarity + UINT32 PchM2Ssd3RstGpio; ///< Offset 2568 Pch M.2 SSD3 Reset Gpio pin + UINT8 PchM2Ssd3RstGpioPolarity; ///< Offset 2572 Pch M.2 SSD3 Reset Gpio pin polarity + // + // XTU SMI base address + // + UINT32 XtuSmiMemoryAddress; ///< Offset 2573 XTU SMI memory in ACPI NVS + UINT8 Reserved19[285]; ///< Offset 2577:2861 + UINT8 MipiCamLink0DD_LanesClkDivision; ///< Offset 2862 LanesClockDivision + UINT8 MipiCamLink1DD_LanesClkDivision; ///< Offset 2863 LanesClockDivision + UINT8 MipiCamLink2DD_LanesClkDivision; ///< Offset 2864 LanesClockDivision + UINT8 MipiCamLink3DD_LanesClkDivision; ///< Offset 2865 LanesClockDivision + UINT8 MipiCamLink4DD_LanesClkDivision; ///< Offset 2866 LanesClockDivision + UINT8 MipiCamLink5DD_LanesClkDivision; ///< Offset 2867 LanesClockDivision + UINT32 POVP; ///< Offset 2868 USBC_PSON_OVERRIDE_N Input pin + UINT32 PSG1; ///< Offset 2872 S0IX_EN_TRY_REQ Output pin + UINT32 PSG2; ///< Offset 2876 S0IX_EN_TRY_ACK Input pin + UINT32 PPOE; ///< Offset 2880 Option to enable/disable TCSS PD PS_ON + UINT8 CvfUsbPort; ///< Offset 2884 CVF USB port number + UINT64 DgBaseAddress; ///< Offset 2885 DG PCIe Base Address + UINT32 DgOpRegionAddress; ///< Offset 2893 DG OpRegion Base Address + UINT32 LidSwitchWakeGpio; ///< Offset 2897 Lid Switch Wake Gpio + UINT8 PreBootCmMode; ///< Offset 2901 USB4 CM mode information in Pre-Boot + UINT8 CmTbtMask; ///< Offset 2902 Indicate enabled dTBT and iTBT for CM + // UCSI/UCMX Driver Support. 0: Force Disable, 1: UCSI Driver support, 2: UCMX Driver support. + UINT32 FoxLanWakeGpio; ///< Offset 2903 Foxville I225 Wake Gpio pin + UINT32 FoxLanRstGpio; ///< Offset 2907 Foxville I225 Reset Gpio pin + UINT8 FoxLanRstGpioPolarity; ///< Offset 2911 Foxville I225 Reset Gpio pin polarity + UINT32 FoxLanDisableNGpio; ///< Offset 2912 Foxville I225 Disable N Gpio pin + UINT8 FoxLanDisableNGpioPolarity; ///< Offset 2916 Foxville I225 Disable N Gpio pin polarity + UINT8 FoxLanSupport; ///< Offset 2917 Foxville I225 support configuration + UINT8 FoxLanRpNumber; ///< Offset 2918 Foxville I225 PCIe Root Port Number + UINT8 DPIW; ///< Offset 2919 DPin Dynamic Switch + UINT32 DPG1; ///< Offset 2920 PcdDpMuxGpio + // + // Data Role Swap: + // + UINT8 UsbcDataRoleSwap; ///< Offset 2924 Usbc Data Role Swap + UINT8 Usb4CmSwitchEnable; ///< Offset 2925 USB4 CM mode switch is enabled/disabled + //Flash ID support for discrete flash solution + UINT8 MipiCamLink0DD_FlashID; ///< Offset 2926 Flash ID for Link0 + UINT8 MipiCamLink1DD_FlashID; ///< Offset 2927 Flash ID for Link1 + UINT8 MipiCamLink2DD_FlashID; ///< Offset 2928 Flash ID for Link2 + UINT8 MipiCamLink3DD_FlashID; ///< Offset 2929 Flash ID for Link3 + UINT8 MipiCamLink4DD_FlashID; ///< Offset 2930 Flash ID for Link4 + UINT8 MipiCamLink5DD_FlashID; ///< Offset 2931 Flash ID for Link5 + //ZPODD support + UINT32 ZpoddDAGpio; ///< Offset 2932 ZPODD device attention gpio + UINT32 ZpoddPRGpio; ///< Offset 2936 ZPODD device present gpio + UINT32 ZpoddPWGpio; ///< Offset 2940 ZPODD device power gpio + UINT8 ZpoddPWGpioPolarity; ///< Offset 2944 ZPODD device power gpio polarity + UINT8 PcdH8S2113UAR; ///< Offset 2945 H8S2113 UAR + // Onboard MR support (for ADL S8 only) + UINT32 OnBoardMr1PowerEnableGpio; ///< Offset 2946 Onboard MR 1 Power Enable Gpio pin + UINT8 OnBoardMr1PowerEnableGpioPolarity; ///< Offset 2950 Onboard MR 1 Power Enable Gpio pin polarity + UINT32 OnBoardMr1RstGpio; ///< Offset 2951 Onboard MR 1 Rest Gpio pin + UINT8 OnBoardMr1RstGpioPolarity; ///< Offset 2955 Onboard MR 1 Rest Gpio pin polarity + UINT32 OnBoardMr1WakeGpio; ///< Offset 2956 Onboard MR 1 Wake Gpio pin + UINT8 OnBoardMr1RpNumber; ///< Offset 2960 Onboard MR 1 Root Port Number + // Onboard MR support + UINT32 OnBoardMr2PowerEnableGpio; ///< Offset 2961 Onboard MR 2 Power Enable Gpio pin + UINT8 OnBoardMr2PowerEnableGpioPolarity; ///< Offset 2965 Onboard MR 2 Power Enable Gpio pin polarity + UINT32 OnBoardMr2RstGpio; ///< Offset 2966 Onboard MR 2 Rest Gpio pin + UINT8 OnBoardMr2RstGpioPolarity; ///< Offset 2970 Onboard MR 2 Rest Gpio pin polarity + UINT32 OnBoardMr2WakeGpio; ///< Offset 2971 Onboard MR 2 Wake Gpio pin + UINT8 OnBoardMr2RpNumber; ///< Offset 2975 Onboard MR 2 Root Port Number + UINT8 Rp08D3ColdSupport; ///< Offset 2976 RP08 D3Cold Support + UINT32 DisplayMuxGpioNo; ///< Offset 2977 Display Mux GPIO pin + UINT8 DgBrightnessPercentage; ///< Offset 2981 DG eDP Brightness Level Percentage + UINT8 DgNumberOfValidDeviceId; ///< Offset 2982 DG Number of Valid Device IDs + UINT32 DgDeviceId1; ///< Offset 2983 DG Device ID 1 + UINT32 DgDeviceId2; ///< Offset 2987 DG Device ID 2 + UINT32 DgDeviceId3; ///< Offset 2991 DG Device ID 3 + UINT32 DgDeviceId4; ///< Offset 2995 DG Device ID 4 + UINT32 DgDeviceId5; ///< Offset 2999 DG Device ID 5 + UINT32 DgDeviceId6; ///< Offset 3003 DG Device ID 6 + UINT32 DgDeviceId7; ///< Offset 3007 DG Device ID 7 + UINT32 DgDeviceId8; ///< Offset 3011 DG Device ID 8 + UINT32 DgDeviceId9; ///< Offset 3015 DG Device ID 9 + UINT32 DgDeviceId10; ///< Offset 3019 DG Device ID 10 + UINT32 DgDeviceId11; ///< Offset 3023 DG Device ID 11 + UINT32 DgDeviceId12; ///< Offset 3027 DG Device ID 12 + UINT32 DgDeviceId13; ///< Offset 3031 DG Device ID 13 + UINT32 DgDeviceId14; ///< Offset 3035 DG Device ID 14 + UINT32 DgDeviceId15; ///< Offset 3039 DG Device ID 15 + UINT32 DgDeviceIdX; ///< Offset 3043 DG Device ID for eDP device + UINT8 DgDisplaySupportFlag; ///< Offset 3047 _DOS DG Display Support Flag. + UINT8 ZpoddPortBitmask; ///< Offset 3048 Bitmask of port support zpodd +} PLATFORM_NVS_AREA; + +#pragma pack(pop) +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h new file mode 100644 index 0000000000..07657c219f --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h @@ -0,0 +1,39 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _PLATFORMPOSTCODE_H_ +#define _PLATFORMPOSTCODE_H_ + +// +// GENERAL USAGE GUIDELINES +// + +/** +[definition] +PostCode = XYZZ +X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE +Y - "6"=platform driver, "5"=board driver +ZZ - "00"=entry, "7F"=exit + - 1 - board init premem: entry/exit (0xD500/0xD57F) + - 2 - platform init premem: entry/exit (0xD600/0xD67F) + - 3 - board init postmem: entry/exit (0x9500/0x957F) + - 4 - platform init postmem: entry/exit (0x9600/0x967F) + - 5 - board init DXE: entry/exit (0x7500/0x757F) + - 6 - platform init DXE: entry/exit (0x7600/0x767F) + - 7 - platform SMM init: entry/exit (0x8600/0x867F) + - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC + - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC + - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with ACPI _PTS PC +*/ + +#define PLATFORM_INIT_PREMEM_ENTRY 0xD600 +#define PLATFORM_INIT_PREMEM_EXIT 0xD67F +#define PLATFORM_INIT_POSTMEM_ENTRY 0x9600 +#define PLATFORM_INIT_POSTMEM_EXIT 0x967F +#define PLATFORM_SMM_INIT_ENTRY 0x8600 +#define PLATFORM_SMM_INIT_EXIT 0x867F + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h new file mode 100644 index 0000000000..c9ace9d910 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h @@ -0,0 +1,48 @@ +/** @file + Macros for platform to update different types of policy. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _POLICY_UPDATE_MACRO_H_ +#define _POLICY_UPDATE_MACRO_H_ + +#ifdef UPDATE_POLICY +#undef UPDATE_POLICY +#endif + +#ifdef COPY_POLICY +#undef COPY_POLICY +#endif + +#ifdef GET_POLICY +#undef GET_POLICY +#endif + +#ifdef AND_POLICY +#undef AND_POLICY +#endif + +#ifdef OR_POLICY +#undef OR_POLICY +#endif + +#define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField = Value; +#define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem (ConfigField, Value, Size); +#define GET_POLICY(UpdField, ConfigField, Value) Value = ConfigField; +#define AND_POLICY(UpdField, ConfigField, Value) ConfigField &= Value; +#define OR_POLICY(UpdField, ConfigField, Value) ConfigField |= Value; +// +// Compare Policy Default and Setup Default when FirstBoot and RvpSupport +// + +#define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value) {\ + UPDATE_POLICY(UpdField, ConfigField, Value);\ +} +#define COMPARE_UPDATE_POLICY_ARRAY(UpdField, ConfigField, Value, ArrayIndex) {\ + UPDATE_POLICY(UpdField, ConfigField, Value);\ +} + +#endif //_POLICY_UPDATE_MACRO_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h new file mode 100644 index 0000000000..6efd40c2b6 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h @@ -0,0 +1,36 @@ +/** @file + This file defines the Platform NVS Area Protocol. + + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_NVS_AREA_H_ +#define _PLATFORM_NVS_AREA_H_ + +// +// Platform NVS Area definition +// +#include <PlatformNvsAreaDef.h> + +// +// Includes +// +#define PLATFORM_NVS_DEVICE_ENABLE 1 +#define PLATFORM_NVS_DEVICE_DISABLE 0 + +// +// Forward reference for pure ANSI compatibility +// +typedef struct _PLATFORM_NVS_AREA_PROTOCOL PLATFORM_NVS_AREA_PROTOCOL; + + +// +// Platform NVS Area Protocol +// +typedef struct _PLATFORM_NVS_AREA_PROTOCOL { + PLATFORM_NVS_AREA *Area; +} PLATFORM_NVS_AREA_PROTOCOL; + +#endif // _PLATFORM_NVS_AREA_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec new file mode 100644 index 0000000000..d24daf30b5 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec @@ -0,0 +1,605 @@ +## @file +# +# The DEC files are used by the utilities that parse DSC and +# INF files to generate AutoGen.c and AutoGen.h files +# for the build infrastructure. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +DEC_SPECIFICATION = 0x00010017 +PACKAGE_NAME = BoardPkg +PACKAGE_VERSION = 0.1 +PACKAGE_GUID = A840FA72-FBF7-4357-B301-DAE2233F14AB + +[Includes] +Include +Acpi/AcpiTables +Acpi/AcpiTables/Include +Acpi/AcpiTables/Dsdt +Acpi/AcpiTables/Mcfg + +[Guids] + gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} + gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} + gPlatformInitFvLocationGuid = {0xa564010a, 0x1d90, 0x4b1c, {0x8d, 0x10, 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}} + gAcpiTableStorageGuid = {0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd}} + gRcAcpiTableStorageGuid = {0x6b5c8fe5, 0x70dd, 0x4e17, {0xbf, 0xf4, 0xd2, 0x1c, 0x26, 0x58, 0x6e, 0xb3}} + gVpdFfsGuid = {0x338FA35A, 0xCA4A, 0x4DBC, {0xA6, 0xF4, 0x9B, 0xD1, 0x59, 0x3B, 0x61, 0xBC}} + gS3MemoryVariableGuid = {0x973218b9, 0x1697, 0x432a, {0x8b, 0x34, 0x48, 0x84, 0xb5, 0xdf, 0xb3, 0x59}} + gSetupDataHobGuid = {0x822a9b23, 0x2386, 0x4377, { 0xb7, 0x05, 0x87, 0x78, 0xc1, 0xb8, 0xb3, 0x95}} + gBoardInfoVariableGuid = {0x1E785E1A, 0x8EC4, 0x49E4, {0x82, 0x75, 0xFB, 0xBD, 0xED, 0xED, 0x18, 0xE7}} + gDebugConfigVariableGuid = {0xDE0A5E74, 0x4E3E, 0x3D96, {0xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}} + gBiosInfoRecoveryGuid = {0x230f6679, 0xf703, 0x4dc2, {0xb2, 0xb7, 0x41, 0xc6, 0x70, 0xbc, 0xc0, 0xd1}} + gMemoryConfigVariableGuid = {0xc94f8c4d, 0x9b9a, 0x45fe, {0x8a, 0x55, 0x23, 0x8b, 0x67, 0x30, 0x26, 0x43}} + +## Include/BootState.h + gBootStateGuid = {0x60b5e939, 0x0fcf, 0x4227, {0xba, 0x83, 0x6b, 0xbe, 0xd4, 0x5b, 0xc0, 0xe3}} + +# +# FvImage File +# + gFvAdvancedFileGuid = {0xAD198BA5, 0xC330, 0x41CD, {0xB0, 0x97, 0x16, 0x48, 0x83, 0x28, 0xB7, 0x98}} + gFvOsBootFileGuid = {0xB9020753, 0x84A8, 0x4BB6, {0x94, 0x7C, 0xCE, 0x7D, 0x41, 0xF5, 0xCE, 0x39}} + gFvUefiBootFileGuid = {0x9E21FD93, 0x9C72, 0x4c15, {0x8C, 0x4B, 0xE7, 0x7F, 0x1D, 0xB2, 0xD7, 0x92}} + gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} + + # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/Shell.inf. + gUefiShellFileGuid = {0x7c04a583, 0x9e3e, 0x4f1c, {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}} + +[Protocols] + gPlatformNvsAreaProtocolGuid = {0xc77ae556, 0x40a3, 0x41c0, {0xac, 0xe6, 0x71, 0x43, 0x8c, 0x60, 0xf8, 0x71}} + gFvAppDispatchFlagProtocolGuid = {0x47458821, 0x44a3, 0x43f6, {0x90, 0xda, 0xdf, 0xdf, 0xce, 0x62, 0xf4, 0xfc}} + +[Ppis] + gReadyForGopConfigPpiGuid = {0x5f252c18, 0x1781, 0x4290, {0xa7, 0xb6, 0xfd, 0x99, 0x63, 0x4c, 0x6a, 0x8a}} + gPeiFvCnvDispatchFlagPpiGuid = {0x2ea45093, 0xa4e6, 0x42ac, {0x86, 0xcf, 0x5e, 0xc6, 0xbf, 0xfb, 0x88, 0x85}} + gPatchConfigurationDataPreMemPpiGuid = {0xa09b1a0c, 0x690c, 0x4d48, {0xa8, 0x98, 0xa1, 0x2c, 0x94, 0x26, 0xd7, 0x06}} + gSetupVariablesReadyPpiGuid = {0xda549f2b, 0xb2ed, 0x43a2, {0xb2, 0x4d, 0xc3, 0x67, 0x67, 0xa8, 0xcf, 0x27}} + + +[LibraryClasses] + +[PcdsFixedAtBuild, PcdsPatchableInModule] +## +## PcdSmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS, +## values 0-0x7F will be treated as disable FVI reporting. +## FVI structure uses it as SMBIOS OEM type to provide version information. +## +gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo|0xDD|UINT8|0x20000001 + +[PcdsFixedAtBuild] + gBoardModuleTokenSpaceGuid.PcdDefaultBoardId|0|UINT16|0x10101009 + + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001010 + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001011 + + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018 + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F + + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000001C + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D + + gBoardModuleTokenSpaceGuid.PcdSetupEnable |FALSE|BOOLEAN|0xF0000027 + gBoardModuleTokenSpaceGuid.PcdModularCryptoEnable |FALSE|BOOLEAN|0xF000001B + + ## + ## The Flash PCDs will be patched based on FDF definitions during build. + ## Set them to 0 here to prevent confusion. + ## + + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000000|UINT32|0x20000040 + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize|0x00000000|UINT32|0x20000041 + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|0x00000000|UINT32|0x20000042 + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x2000004C + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x2000004D + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32|0x2000004E + gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionOffset|0x00000000|UINT32|0x20000050 + gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionSizeInUse|0x00000000|UINT32|0x20000051 + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase|0x00000000|UINT32|0x20000052 + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize|0x00000000|UINT32|0x20000054 + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase|0x00000000|UINT32|0x20000055 + gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize|0x00000000|UINT32|0x20000057 + + gBoardModuleTokenSpaceGuid.PcdSipkgBinaryEnable |FALSE|BOOLEAN|0xF0000A50 + gBoardModuleTokenSpaceGuid.PcdFlashObbSize|0x00000000|UINT32|0xF0000A53 + gBoardModuleTokenSpaceGuid.PcdFlashIbbOffset|0x00000000|UINT32|0xF0000A58 + gBoardModuleTokenSpaceGuid.PcdFlashIbbSize|0x00000000|UINT32|0xF0000A59 + gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdOffset|0x00000000|UINT32|0x20000A5E + gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdSize|0x00000000|UINT32|0x20000A5F + gBoardModuleTokenSpaceGuid.PcdFlashIbbROffset|0x00000000|UINT32|0x20000A61 + +#(ACPI.inf) + gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9000000B + gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000000D + gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 + gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 + gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E + +#(PeiMultiBoardInitPreMemLib.inf) + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort|0x2F|UINT16|0x9000001A + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort|0x2E|UINT16|0x9000001B + +#(BaseMmioInitLib.inf) +gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFEDA0000|UINT64|0x90000003 +## From Client SNB EDS 0.7v3, 4KB window +gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFEDA1000|UINT64|0x90000005 + +#(OpenBoardPlatformInitPreMem.inf) +gPlatformModuleTokenSpaceGuid.PcdRamDebugEnable |FALSE|BOOLEAN|0xF0000094 +gPlatformModuleTokenSpaceGuid.PcdSerialPortEnable |FALSE|BOOLEAN|0xF000002D + +#(OpenBoardPlatformInitSmm.inf) +gPlatformModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 + +## This PCD specifies whether StatusCode is reported via SerialIoUart +gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|FALSE|BOOLEAN|0xFF000002 + +## This flag is used to initialize debug output interface. +# BIT0 - RAM debug interface. +# BIT1 - UART debug interface. +# BIT2 - USB debug interface. +# BIT3 - USB3 debug interface. +# BIT4 - Serial IO debug interface. +# BIT5 - TraceHub debug interface. +# BIT6 - Reserved. +# BIT7 - CMOS control. +gPlatformModuleTokenSpaceGuid.PcdStatusCodeFlags|0x82|UINT8|0xF0000111 + +gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xAF000000|UINT64|0x9000000F +gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xB0000000|UINT64|0x90000010 + +gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x90000009 +gPlatformModuleTokenSpaceGuid.PcdExtendedBiosRegionSupport|FALSE|BOOLEAN|0xF00000A3 + +gPlatformModuleTokenSpaceGuid.PcdLzmaEnable |FALSE|BOOLEAN|0xF000002B +gPlatformModuleTokenSpaceGuid.PcdSymbolInReleaseEnable |FALSE|BOOLEAN|0xF0000063 +gPlatformModuleTokenSpaceGuid.PcdDeprecatedFunctionRemove |TRUE|BOOLEAN|0xF000008D + +## Enable/Disable the ECC feature in openssl library. The default is disabled. +# If ECC feature is disabled, all related source files will not be compiled. +gEfiCryptoPkgTokenSpaceGuid.PcdOpensslEcEnabled|FALSE|BOOLEAN|0x0000003 + + +[PcdsDynamic, PcdsPatchableInModule] + +[PcdsDynamic] + + # PCH Misc Configuration + gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065 + gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110 + + # DRAM Configuration + gBoardModuleTokenSpaceGuid.PcdMrcSpdData00|0|UINT32|0x00000170 + gBoardModuleTokenSpaceGuid.PcdMrcSpdData01|0|UINT32|0x00000171 + gBoardModuleTokenSpaceGuid.PcdMrcSpdData10|0|UINT32|0x00000172 + gBoardModuleTokenSpaceGuid.PcdMrcSpdData11|0|UINT32|0x00000173 + gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174 + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000175 + gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram|0|UINT32|0x00000072 + gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize|0|UINT16|0x00000073 + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000199 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000019A + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000019B + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000019C + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4|0|UINT8|0x0000019D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5|0|UINT8|0x0000019E + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6|0|UINT8|0x0000019F + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7|0|UINT8|0x000001A0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8|0|UINT8|0x000001A1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9|0|UINT8|0x000001A2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10|0|UINT8|0x000001A3 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11|0|UINT8|0x000001A4 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12|0|UINT8|0x000001A5 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13|0|UINT8|0x000001A6 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14|0|UINT8|0x000001A7 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15|0|UINT8|0x000001A8 + + # CA Vref Configuration + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D + + # Root Port Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E + gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F + gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0 + gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1 + gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2 + gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3 + gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4 + gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5 + gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6 + gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7 + gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8 + gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9 + gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA + gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB + gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC + gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD + gBoardModuleTokenSpaceGuid.PcdPcieClock16|0|UINT64|0x000000AE + gBoardModuleTokenSpaceGuid.PcdPcieClock17|0|UINT64|0x000000AF + + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB + + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdCpuXhciPortSupportMap|0|UINT8|0x00100031 + gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable|0|UINT8|0x00100032 + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033 + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034 + + # MISC + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE + gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E + gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x00000100 + + # STAT + gBoardModuleTokenSpaceGuid.PcdSataPortsEnable0|0|UINT8|0x000000F0 + + # CPU + gBoardModuleTokenSpaceGuid.PcdCpuRatio|0x0|UINT8|0x00000200 + + # MISC + gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000A09 + gBoardModuleTokenSpaceGuid.PcdStackBase|0x0|UINT32|0x40000A10 + gBoardModuleTokenSpaceGuid.PcdStackSize|0x0|UINT32|0x40000A11 + gBoardModuleTokenSpaceGuid.PcdNvsBufferPtr|0x0|UINT32|0x40000A12 + gBoardModuleTokenSpaceGuid.PcdCleanMemory|0x0|UINT8|0x40000A13 + + # + # The PCD which is defined to enable/disable the SATA LED function. + # + gBoardModuleTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010111F + + # + # The PCD which is defined to enable/disable the VR Alert function. + # + gBoardModuleTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020 + + # + # This PCD is defined to enable/disable TCSS BIOS handshake for PMC-PD solution + # + gBoardModuleTokenSpaceGuid.PcdBoardPmcPdEnable|TRUE|BOOLEAN|0x00101024 + + # TouchPanel + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1|0|UINT32|0x00000048 + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1Size|0|UINT16|0x00000049 + + + # SA Misc Configuration + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067 + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x0000A101 + gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask|0|UINT8|0x0000A103 + gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc|0|UINT8|0x0000A104 + gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss|0|UINT8|0x0000A105 + + #CVF GPIO configuration + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvf|0|UINT32|0x0000B101 + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvfSize|0|UINT16|0x0000B102 + + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|0x40000014 + + # Board Information + gBoardModuleTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011 + gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012 + gBoardModuleTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014 + gBoardModuleTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015 + gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT16|0x00101016 + gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT16|0x00101017 + gBoardModuleTokenSpaceGuid.PcdBoardId|0|UINT16|0x00101018 + gBoardModuleTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019 + gBoardModuleTokenSpaceGuid.PcdSkuType|0x0|UINT8|0x0010101F + gBoardModuleTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004 + gBoardModuleTokenSpaceGuid.PcdDisplayId|0x0|UINT16|0x00101032 + + # MRC Config + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000A68 + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000A69 + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x00000A6A + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x00000A6B + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x00000A6C + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x00000A6D + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x00000A6E + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x00000A6F + gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig|0|UINT8|0x00000A73 + gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror|0|UINT8|0x00000A74 + gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000A78 + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb2OverCurrentPinTable|0|UINT32|0x000000BC + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb3OverCurrentPinTable|0|UINT32|0x000000BE + + # Pch SerialIo I2c Pads Termination + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x00000020 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x00000021 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x00000022 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x00000023 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x00000030 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x00000031 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm|0x1|UINT8|0x00000032 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm|0x1|UINT8|0x00000033 + + # UCMC GPIO Table + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio1|0|UINT32|0x0000011B + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio2|0|UINT32|0x0000011C + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio3|0|UINT32|0x0000011D + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio4|0|UINT32|0x0000011E + + + gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205 + + #PlatformInfoPcd + gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101000 + + # + # The PCD defines the I2C bus number to which PSS chip connected. + # + gBoardModuleTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101025 + gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber|0x05|UINT8|0x00101026 + gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101027 + + # PCIE SLOT 1 - X4 CONNECTOR RTD3 + gBoardModuleTokenSpaceGuid.PcdPcieSlot1GpioSupport|0|UINT8|0x00000A79 + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableExpanderNo|0|UINT8|0x00000A7D + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableGpioNo|0|UINT32|0x00000A7E + gBoardModuleTokenSpaceGuid.PcdPcieSlot1WakeGpioPin|0x0|UINT32|0x00000A80 + gBoardModuleTokenSpaceGuid.PcdDg1VramSRGpio|0x0|UINT32|0x00000A82 + + + # PCIE SLOT 2 - X4 CONNECTOR RTD3 + gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot2PwrEnableGpioNo|0|UINT32|0x00000084 + gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot2PwrEnableGpioPolarity|0|BOOLEAN|0x00000085 + gBoardModuleTokenSpaceGuid.PcdPcieSlot2WakeGpioPin|0|UINT32|0x00000088 + gBoardModuleTokenSpaceGuid.PcdPcieSlot2RootPort|0|UINT8|0x0000008A + + # CPU M.2 SSD Slot RTD3 + gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioNo|0|UINT32|0x0000008B + gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioPolarity|0|BOOLEAN|0x0000008D + gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioNo|0|UINT32|0x00000101 + gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioPolarity|0|BOOLEAN|0x00000109 + + # CPU Peg DG Slot RTD3 + gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioNo|0|UINT32|0x00000105 + gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioPolarity|0|BOOLEAN|0x00000107 + gBoardModuleTokenSpaceGuid.PcdPcieDG2WakeGpioPin|0|UINT32|0x00000113 + + # PCH SATA port RTD3 + gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioNo|0|UINT32|0x0000008F + gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioPolarity|0|BOOLEAN|0x00000400 + + + # DXE PCDs + gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature|0x0|UINT64|0x00100250 + gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203 + gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204 + gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature|FALSE|BOOLEAN|0x00100123 + gBoardModuleTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221 + + + # ASL PCDs + gBoardModuleTokenSpaceGuid.PcdBatteryPresent |0x0|UINT8|0x00100124 + gBoardModuleTokenSpaceGuid.PcdRealBattery1Control |0x00|UINT8|0x00100103 + gBoardModuleTokenSpaceGuid.PcdRealBattery2Control |0x00|UINT8|0x00100104 + gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM |FALSE|BOOLEAN|0x00100107 + gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO |FALSE|BOOLEAN|0x00100108 + gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|BOOLEAN|0x00100109 + gBoardModuleTokenSpaceGuid.PcdH8S2113SIO |FALSE|BOOLEAN|0x0010010A + gBoardModuleTokenSpaceGuid.PcdH8S2113UAR |FALSE|BOOLEAN|0x0010010B + gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin |0x00|UINT32|0x00100111 + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport |FALSE|BOOLEAN|0x00100119 + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport |FALSE|BOOLEAN|0x0010011A + gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport |FALSE|BOOLEAN|0x0010011B + gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport |FALSE|BOOLEAN|0x0010011C + gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport |FALSE|BOOLEAN|0x0010011D + gBoardModuleTokenSpaceGuid.PcdVirtualGpioButtonSupport |FALSE|BOOLEAN|0x0010011E + gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin |0x00|UINT32|0x00100120 + gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport |FALSE|BOOLEAN|0x00100121 + gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport |FALSE|BOOLEAN|0x00100122 + + # Policy Default Check with Setup Necessary + gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsFirstBoot|0|BOOLEAN|0x00000275 + gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsRvpSupport|0|BOOLEAN|0x00000276 + gBoardModuleTokenSpaceGuid.PcdPolicyCheckPcdInitDone|0|BOOLEAN|0x00000277 + +[PcdsDynamicEx] +# Flag to Disable Vpd Gpio +gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable|FALSE|BOOLEAN|0x50000015 +# Pre-Mem GPIO table + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG_ARRAY|0x50000017 { + <HeaderFiles> + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + PlatformGpioConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + + gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG[]|0x50000018 { + <HeaderFiles> + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + Library/GpioConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# GPIO table + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|{0}|GPIO_INIT_CONFIG_ARRAY|0x50000019 { + <HeaderFiles> + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + PlatformGpioConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|{0}|GPIO_INIT_CONFIG[]|0x5000001C { + <HeaderFiles> + Pins/GpioPinsVer2Lp.h + Library/GpioConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# PCIE CLOCKS USAGE + gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|{0}|PCIE_CLOCKS_USAGE|0x50000022 { + <HeaderFiles> + PlatformBoardConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# USB2 OC MAPPING + gBoardModuleTokenSpaceGuid.VpdPcdUSB2OCMap|{0}|USB_OC_MAP_TABLE|0x50000023 { + <HeaderFiles> + PlatformBoardConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# USB3 OC MAPPING + gBoardModuleTokenSpaceGuid.VpdPcdUSB3OCMap|{0}|USB_OC_MAP_TABLE|0x50000024 { + <HeaderFiles> + PlatformBoardConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + + +#SBC SPD DATA + gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|{0}|SPD_DATA|0x50000025 { + <HeaderFiles> + PlatformBoardConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# SBC MRC DQS MAPPING + gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram|{0}|MRC_DQS|0x50000026 { + <HeaderFiles> + PlatformBoardConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# SBC MRC DQ MAPPING + gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|{0}|MRC_DQ|0x50000027 { + <HeaderFiles> + PlatformBoardConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# CPU USB3 OC MAPPING + gBoardModuleTokenSpaceGuid.VpdPcdCpuUsb3OcMap|{0}|USB_OC_MAP_TABLE|0x50000028 { + <HeaderFiles> + PlatformBoardConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# ACPI data + gBoardModuleTokenSpaceGuid.PcdBoardAcpiData|{0}|VOID*|0x5000001A + +# Early Pre-Mem GPIO table + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem|{0}|GPIO_INIT_CONFIG_ARRAY|0x5000001B { + <HeaderFiles> + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + PlatformGpioConfig.h + <Packages> + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderLakeOpenBoardPkg/OpenBoardPkg.dec +} + + # Onboard MR 1 RTD3 (for ADL S8 only, used when dTBT is enabled) + gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioNo|0|UINT32|0x00000149 + gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioPolarity|0|BOOLEAN|0x00000150 + gBoardModuleTokenSpaceGuid.PcdOnBoardMr1WakeGpioPin|0|UINT32|0x00000153 + gBoardModuleTokenSpaceGuid.PcdOnBoardMr1RootPort|0|UINT8|0x00000154 + + # Onboard MR 2 RTD3 (Used when dTBT is enabled) + gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioNo|0|UINT32|0x00000155 + gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioPolarity|0|BOOLEAN|0x00000156 + gBoardModuleTokenSpaceGuid.PcdOnBoardMr2WakeGpioPin|0|UINT32|0x00000159 + gBoardModuleTokenSpaceGuid.PcdOnBoardMr2RootPort|0|UINT8|0x00000160 + +[PcdsDynamic, PcdsDynamicEx] + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] + gBoardModuleTokenSpaceGuid.PcdUefiShellEnable |FALSE|BOOLEAN|0xF0000B53 + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |FALSE|BOOLEAN|0xF0000B54 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT) + # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver. + # This MIPI GUID can be updated by patching or runtime if platform support multiple VBT configurations. + # @Prompt GUID of the FFS which contains the Graphics Video BIOS Table (VBT) + # { 0x8958d092, 0x7b26, 0x4e47, 0xbb, 0x98, 0x16, 0xae, 0x2d, 0xc3, 0x15, 0xa2 } + gBoardModuleTokenSpaceGuid.PcdVbtMipiGuid|{ 0x92, 0xd0, 0x58, 0x89, 0x26, 0x7b, 0x47, 0x4e, 0xbb, 0x98, 0x16, 0xae, 0x2d, 0xc3, 0x15, 0xa2 }|VOID*|0x00000001 + + ## PCDs for the MMIO base address range (default 1M) for ATA AHCI host controller used in PEI phase + gPlatformModuleTokenSpaceGuid.PcdAhciPeiMmioBase|0xD1000000|UINT32|0x0000C10E + gPlatformModuleTokenSpaceGuid.PcdAhciPeiMmioLimit|0xD10FFFFF|UINT32|0x0000C10F + + # PCDs for the MMIO base address range (default 4M) for NVM Express host controller used in PEI phase + # @Prompt Temporary mmio base address of NVME host controller. + gPlatformModuleTokenSpaceGuid.PcdNvmeHcPeiMmioBase |0xFFFFFFFF|UINT32|0x0000C110 + # @Prompt Temporary mmio address limitation of NVME host controller. + gPlatformModuleTokenSpaceGuid.PcdNvmeHcPeiMmioLimit|0xFFFFFFFF|UINT32|0x0000C111 + + # PCDs for the MMIO base address range (default 4M) for UFS host controller used in PEI phase + # @Prompt Temporary mmio base address of UFS host controller. + gPlatformModuleTokenSpaceGuid.PcdUfsPeiHcMmioBase |0xFFFFFFFF|UINT32|0x0000C112 + + # + # This PCD use for UFS BlockIo maximum read size from deivce in PEI phase. + # Value need to take the Dma Buffer Size into account. + # Must be a multiple of the intrinsic block size of the device. + # + gPlatformModuleTokenSpaceGuid.PcdUfsReadPeiMaxTransferSize|0x00001000|UINT32|0x0000C113 + + + ## This PCD defines initial setting of TCG2 Persistent Firmware Management Flags + # PCD can be configured for different settings in different scenarios + # Default setting is TCG2_BIOS_TPM_MANAGEMENT_FLAG_DEFAULT | TCG2_BIOS_STORAGE_MANAGEMENT_FLAG_DEFAULT + # @Prompt Initial setting of TCG2 Persistent Firmware Management Flags + # Enabled PPI for PPRequiredForTurnOff, PPRequiredForChangeEPS, PPRequiredForChangePCRs, PPRequiredForEnable_BlockSIDFunc, PPRequiredForDisable_BlockSIDFunc + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x300E0|UINT32|0x0001001B + -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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