On Thu, May 18, 2023 at 12:16:21AM +0100, Pedro Falcato wrote:
> On Wed, May 17, 2023 at 11:24 AM Gerd Hoffmann <kra...@redhat.com> wrote:
> The Intel SDM and AMD manuals both mention possible bad side effects
> for having large pages (2MB/4MB/1GB) spanning multiple MTRRs.
qemu takes care to use gigabyte-alignment for guest RAM for performance
reasons. Unless you are explicitly creating something unusual the
memory layout below 4G is 2G RAM + 2G MMIO (q35 machine type) or 3G RAM
+ 1G MMIO (pc machine type).
edk2 creates mtrr uncachable entries for the mmio regions (both 32bit
and 64bit window). On q35 it looks like this:
reg00: base=0x080000000 ( 2048MB), size= 2048MB, count=1: uncachable
reg01: base=0x7000000000 (458752MB), size=65536MB, count=1: uncachable
Both are gigabyte-aligned and are a multiple of gigabytes in size, so
you simply can't create gigabyte page table entries crossing mtrr entry
borders.
That's relatively recent change though, q35 used to be different, see
commit e4b3fd905a17 ("OvmfPkg/PlatformInitLib: simplify mtrr setup")
> While I don't expect my comment to be a blocker (particularly as other
> OVMF platforms are already using them), I think it's probably a good
> idea to let you know.
Yes, thanks, sure good to know. But I don't expect that being a
problem.
take care,
Gerd
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