Acked-by: Jiewen Yao <jiewen....@intel.com> > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Andrei > Warkentin > Sent: Saturday, April 8, 2023 5:44 AM > To: devel@edk2.groups.io > Cc: Warkentin, Andrei <andrei.warken...@intel.com>; Daniel Schaefer > <g...@danielschaefer.me>; Sunil V L <suni...@ventanamicro.com> > Subject: [edk2-devel] [PATCH v7 3/3] OvmfPkg: RiscVVirt: Add missing > SerialPortInitialize to Sec > > If the SerialPortLib had any initialization needed, this > would be skipped in the RiscVVirt Sec. Follow the example > seen elsewhere (ArmVirtPkg PrePi). > > Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec, > yet using DBCN elsewhere. > > Cc: Daniel Schaefer <g...@danielschaefer.me> > Reviewed-by: Sunil V L <suni...@ventanamicro.com> > Signed-off-by: Andrei Warkentin <andrei.warken...@intel.com> > --- > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + > OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- > 3 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf > b/OvmfPkg/RiscVVirt/Sec/SecMain.inf > index aed35d3af596..0e2a5785e8a4 100644 > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf > @@ -48,6 +48,7 @@ [LibraryClasses] > FdtLib > MemoryAllocationLib > HobLib > + SerialPortLib > > [Ppis] > gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h > b/OvmfPkg/RiscVVirt/Sec/SecMain.h > index 83a8058efe40..7c7650f0d298 100644 > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h > @@ -29,6 +29,7 @@ > #include <Library/PrePiLib.h> > #include <Library/PlatformInitLib.h> > #include <Library/PrePiHobListPointerLib.h> > +#include <Library/SerialPortLib.h> > #include <Register/RiscV64/RiscVImpl.h> > > /** > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c > b/OvmfPkg/RiscVVirt/Sec/SecMain.c > index adf73f2eb66c..b35c77774510 100644 > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c > @@ -1,7 +1,7 @@ > /** @file > RISC-V SEC phase module for Qemu Virt. > > - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR> > + Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> > Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > @@ -57,6 +57,8 @@ SecStartup ( > UINT64 StackBase; > UINT32 StackSize; > > + SerialPortInitialize (); > + > // > // Report Status Code to indicate entering SEC core > // > -- > 2.25.1 > > > > >
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