Currently, in reset vector, pagetable is creating from top to bottom.
It does this way: First a 4K buffer for PML4, then a 4K buffer for
Page-directory pointer table, at last multiples 4K buffers for
Page-Directory. The PML4 have loweset address.
It works. However, if we change it to creating from bottom to top, we
can let the PML4 have the highest address. Also, because after page
table, code layout is fixed(4K for normal code, and another 4K only
contains reset vector code), we can make sure PML4 has a fixed
address in flash, which is 4G-12K
In a work, this patch can improve debuggability by make sure the init
CR3 pointting a fixed address(4G-12K).
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Debkumar De <debkumar...@intel.com>
Cc: Catharine West <catharine.w...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
---
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 3 +-
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 5 ++-
.../ResetVector/Vtf0/X64/PageTables1G.asm | 27 +++++--------
.../ResetVector/Vtf0/X64/PageTables2M.asm | 38 +++++++------------
4 files changed, 30 insertions(+), 43 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
index 87a4125d4b..f3a4fc488b 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
@@ -16,8 +16,9 @@ SetCr3ForPageTables64:
;
; These pages are built into the ROM image in X64/PageTables.asm
+ ; Highest level PageTable is at the highest address
;
- mov eax, ADDR_OF(TopLevelPageDirectory)
+ mov eax, ADDR_OF(EndOfPageTables) - 0x1000
mov cr3, eax
OneTimeCallRet SetCr3ForPageTables64
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index bdea1fb875..62887c4e8e 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -2,7 +2,7 @@
; @file
; This file includes all other code files to assemble the reset vector code
;
-; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -37,6 +37,8 @@
%include "PageTables.inc"
+ALIGN 16
+StartOfPageTables:
%ifdef ARCH_X64
%ifdef PAGE_TABLE_1G
%include "X64/PageTables1G.asm"
@@ -44,6 +46,7 @@
%include "X64/PageTables2M.asm"
%endif
%endif
+EndOfPageTables:
%ifdef DEBUG_PORT80
%include "Port80Debug.asm"
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
index 19bd3d5a92..1802000872 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
@@ -2,7 +2,7 @@
; @file
; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
;
-; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Linear-Address Translation to a 1-GByte Page
;
@@ -22,32 +22,25 @@ BITS 64
PAGE_PRESENT + \
PAGE_SIZE)
-%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
-%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
PAGE_PDP_ATTR)
%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
-ALIGN 16
-
-TopLevelPageDirectory:
-
- ;
- ; Top level Page Directory Pointers (1 * 512GB entry)
- ;
- DQ PDP(0x1000)
-
- TIMES 0x1000-PGTBLS_OFFSET($) DB 0
;
- ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
+ ; Page-directory pointer table Pointers (512 * 1GB entries => 512GB)
;
%assign i 0
%rep 512
DQ PDP_1G(i)
%assign i i+1
%endrep
- TIMES 0x2000-PGTBLS_OFFSET($) DB 0
-EndOfPageTables:
+ ;
+ ; PML4 table Pointers (1 * 512GB entry)
+ ;
+ DQ PDP(0)
+
+ TIMES 0x2000-PGTBLS_OFFSET($) DB 0
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
index b97df384ac..2413f925b2 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
@@ -2,7 +2,7 @@
; @file
; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
;
-; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -21,40 +21,30 @@ BITS 64
PAGE_READ_WRITE + \
PAGE_PRESENT)
-%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
-%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
PAGE_PDP_ATTR)
%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
-TopLevelPageDirectory:
+%assign i 0
+%rep 0x800
+ DQ PTE_2MB(i)
+ %assign i i+1
+%endrep
;
- ; Top level Page Directory Pointers (1 * 512GB entry)
+ ; Page-directory pointer table Pointers (4 * 1GB entries => 4GB)
;
+ DQ PDP(0)
DQ PDP(0x1000)
-
-
- ;
- ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
- ;
- TIMES 0x1000-PGTBLS_OFFSET($) DB 0
-
DQ PDP(0x2000)
DQ PDP(0x3000)
- DQ PDP(0x4000)
- DQ PDP(0x5000)
+ TIMES 0x5000-PGTBLS_OFFSET($) DB 0
;
- ; Page Table Entries (2048 * 2MB entries => 4GB)
+ ; PML4 table Pointers (1 * 512GB entry)
;
- TIMES 0x2000-PGTBLS_OFFSET($) DB 0
-
-%assign i 0
-%rep 0x800
- DQ PTE_2MB(i)
- %assign i i+1
-%endrep
+ DQ PDP(0x4000)
-EndOfPageTables:
+ TIMES 0x6000-PGTBLS_OFFSET($) DB 0
--
2.31.1.windows.1
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