REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391
FSP should support the scenario that CPU microcode already loaded
before calling LoadMicrocodeDefault(), in this case it should return
directly without spending more time.
Also the LoadMicrocodeDefault() should only attempt to load one version
of the microcode for current CPU and return directly without parsing
rest of the microcode in FV.
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Signed-off-by: Chasel Chiu <chasel.c...@intel.com>
---
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 26 ++++++++++++++++++++++----
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 ++++++++++++++++++++++----
2 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 2cff8b3643..79f2a20a2c 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault):
cmp esp, 0
jz ParamError
+ ;
+ ; If microcode already loaded before this function, exit this function with
SUCCESS.
+ ;
+ mov ecx, MSR_IA32_BIOS_SIGN_ID
+ xor eax, eax ; Clear EAX
+ xor edx, edx ; Clear EDX
+ wrmsr ; Load 0 to MSR at 8Bh
+
+ mov eax, 1
+ cpuid
+ mov ecx, MSR_IA32_BIOS_SIGN_ID
+ rdmsr ; Get current microcode signature
+ xor eax, eax
+ test edx, edx
+ jnz Exit2
+
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
; first check UPD header revision
@@ -450,7 +466,7 @@ LoadCheck:
; Verify this microcode update is not already loaded
cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
- je Continue
+ je Done ; if already one version microcode loaded, go to done
LoadMicrocode:
; EAX contains the linear address of the start of the Update Data
@@ -465,10 +481,12 @@ LoadMicrocode:
mov eax, 1
cpuid
-Continue:
- jmp NextMicrocode
-
Done:
+ mov ecx, MSR_IA32_BIOS_SIGN_ID
+ xor eax, eax ; Clear EAX
+ xor edx, edx ; Clear EDX
+ wrmsr ; Load 0 to MSR at 8Bh
+
mov eax, 1
cpuid
mov ecx, MSR_IA32_BIOS_SIGN_ID
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index b32fa32a89..3e40678f47 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault):
jz ParamError
mov rsp, rcx
+ ;
+ ; If microcode already loaded before this function, exit this function with
SUCCESS.
+ ;
+ mov ecx, MSR_IA32_BIOS_SIGN_ID
+ xor eax, eax ; Clear EAX
+ xor edx, edx ; Clear EDX
+ wrmsr ; Load 0 to MSR at 8Bh
+
+ mov eax, 1
+ cpuid
+ mov ecx, MSR_IA32_BIOS_SIGN_ID
+ rdmsr ; Get current microcode signature
+ xor rax, rax
+ test edx, edx
+ jnz Exit2
+
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
; first check UPD header revision
@@ -291,7 +307,7 @@ LoadCheck:
; Verify this microcode update is not already loaded
cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
- je Continue
+ je Done ; if already one version microcode loaded, go to done
LoadMicrocode:
; EAX contains the linear address of the start of the Update Data
@@ -306,10 +322,12 @@ LoadMicrocode:
mov eax, 1
cpuid
-Continue:
- jmp NextMicrocode
-
Done:
+ mov ecx, MSR_IA32_BIOS_SIGN_ID
+ xor eax, eax ; Clear EAX
+ xor edx, edx ; Clear EDX
+ wrmsr ; Load 0 to MSR at 8Bh
+
mov eax, 1
cpuid
mov ecx, MSR_IA32_BIOS_SIGN_ID
--
2.35.0.windows.1
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