Hi Abner, Any plan to support SMBUS system interface (ssif)?
- Tinh On 03/03/2023 09:31, Chang, Abner via groups.io wrote:
From: Abner Chang <abner.ch...@amd.com> BZ #4354 This change adds definitions for IPMI KCS. Signed-off-by: Abner Chang <abner.ch...@amd.com> Cc: Michael D Kinney <michael.d.kin...@intel.com> Cc: Liming Gao <gaolim...@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang....@intel.com> Cc: Nickle Wang <nick...@nvidia.com> Cc: Igor Kulchytskyy <ig...@ami.com> Cc: Isaac Oram <isaac.w.o...@intel.com> Cc: Abdul Lateef Attar <abdullateef.at...@amd.com> --- MdePkg/MdePkg.dec | 5 ++ MdePkg/Include/IndustryStandard/IpmiKcs.h | 72 +++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/IpmiKcs.h diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 3d08f20d15b..0ed033983bf 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -9,6 +9,7 @@ # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP<BR> # Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR> # Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -2332,6 +2333,10 @@ # @Prompt Memory Address of GuidedExtractHandler Table. gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x1000000|UINT64|0x30001015+ ## This value is the IPMI KCS Interface I/O base address used to transmit IPMI commands.+ # @Prompt IPMI KCS Interface I/O Base Address + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsBaseAddress|0xca2|UINT16|0x00000031 + [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This value is used to set the base address of PCI express hierarchy. # @Prompt PCI Express Base Address. diff --git a/MdePkg/Include/IndustryStandard/IpmiKcs.h b/MdePkg/Include/IndustryStandard/IpmiKcs.h new file mode 100644 index 00000000000..2a51698b126 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/IpmiKcs.h @@ -0,0 +1,72 @@ +/** @file + IPMI KCS Register Definitions + + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef IPMI_KCS_H_ +#define IPMI_KCS_H_ + +#define IPMI_KCS_STATUS_REGISTER_OFFSET 1 +#define IPMI_KCS_COMMAND_REGISTER_OFFSET 1 +#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET 0 +#define IPMI_KCS_DATA_IN_REGISTER_OFFSET 0 + +/// +/// IPMI KCS Interface Status Bits +/// +#define IPMI_KCS_OBF BIT0 +#define IPMI_KCS_IBF BIT1 +#define IPMI_KCS_SMS_ATN BIT2 +#define IPMI_KCS_COMMAND_DATA BIT3 +#define IPMI_KCS_OEM1 BIT4 +#define IPMI_KCS_OEM2 BIT5 +#define IPMI_KCS_S0 BIT6 +#define IPMI_KCS_S1 BIT7 + +/// +/// IPMI KCS Interface Control Codes +/// +#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT 0x60 +#define IPMI_KCS_CONTROL_CODE_WRITE_START 0x61 +#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62 +#define IPMI_KCS_CONTROL_CODE_READ 0x68 + +/// +/// Status Codes +/// +#define IPMI_KCS_STATUS_NO_ERROR 0x00 +#define IPMI_KCS_STATUS_ABORT 0x01 +#define IPMI_KCS_STATUS_ILLEGAL 0x02 +#define IPMI_KCS_STATUS_LENGTH_ERROR 0x06 +#define IPMI_KCS_STATUS_UNSPECIFIED 0xFF + +/// +/// KCS Interface State Bit +/// +typedef enum { + IPMI_KCS_IDLE_STATE = 0, + IPMI_KCS_READ_STATE, + IPMI_KCS_WRITE_STATE, + IPMI_KCS_ERROR_STATE +} IPMI_KCS_STATE; + +/// +/// IPMI KCS Interface Request Format +/// +typedef struct { + UINT8 NetFunc; + UINT8 Command; + UINT8 Data[0]; +} IPMI_KCS_RESQUEST_HEADER; + +/// +/// IPMI KCS Interface Response Format +/// +typedef struct { + UINT8 NetFunc; + UINT8 Command; + UINT8 CompletionCode; +} IPMI_KCS_RESPONSE_HEADER; +#endif
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