From: "Chai, Evan" <evan.c...@intel.com>
RiscVSetSupervisorAddressTranslationRegister() should be moved out from
RiscVCpuLib since it had been merged to MdePkg/Include/Library/BaseLib.h,
to avoid a multiple definition problem in building.
Signed-off-by: Evan Chai <evan.c...@intel.com>
---
.../RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h | 4 +---
Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 10 +---------
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index efe85489..3331ea2f 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -2,6 +2,7 @@
RISC-V CPU library definitions.
Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -96,9 +97,6 @@ RiscVReadMachineImplementId (
VOID
);
-VOID
- RiscVSetSupervisorAddressTranslationRegister (UINT64);
-
VOID
RiscVSetSupervisorScratch (UINT64);
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
index e242c9b8..f5bff547 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -3,6 +3,7 @@
// RISC-V CPU functions.
//
// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+// Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -132,12 +133,3 @@ ASM_FUNC (RiscVSetSupervisorStvec)
ASM_FUNC (RiscVGetSupervisorStvec)
csrr a0, RISCV_CSR_SUPERVISOR_STVEC
ret
-
-//
-// Set Supervisor Address Translation and
-// Protection Register.
-//
-ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
- csrw RISCV_CSR_SUPERVISOR_SATP, a0
- ret
-
--
2.34.1
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