Thanks for the review! > Please swap the Present and ReadWrite lines. You should only set > Present after everything else as to avoid explicit caching (TLB and > paging structure) issues. > > Although this whole file is full of spotty behavior. ASSERTS can get > deleted and the file is full of them.
Yes, keeping consistency with the rest of the file was my main motivation for doing things this way. Will add popper error handling bere in V2. > There are plenty of Present = 1 sets before setting other important > bits like RW, which *will* cause you to get bad TLB entries if the CPU > speculates a load/store to that address. ... > *sigh* > In any case, because of that CpuFlushTlb () your patch isn't wrong, > but it should be changed into something more MMU-code natural. Makes sense! Thanks for all this information. Yes, I simply wanted to order setting of the bits exactly as they have been done before in the file. Will adjust in V2 and send a second patch adjusting them for other instances. Mikolaj -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98989): https://edk2.groups.io/g/devel/message/98989 Mute This Topic: https://groups.io/mt/96250316/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
