REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4246
In function InitPaging, NumberOfPml5Entries is calculated by below code
NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);
If the SizeOfMemorySpace is larger than 48, NumberOfPml5Entries will be
larger than 1. However, this doesn't make sense if the hardware doesn't
support 5 level page table.
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Eric Dong <eric.d...@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang....@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index c1efda7126..c597b39b8c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -1,7 +1,7 @@
/** @file
Enable SMM profile.
-Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2012 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -587,15 +587,17 @@ InitPaging (
}
SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;
+ ASSERT (SizeOfMemorySpace <= 52);
+
//
- // Calculate the table entries of PML4E and PDPTE.
+ // Calculate the table entries of PML5E, PML4E and PDPTE.
//
NumberOfPml5Entries = 1;
- if (SizeOfMemorySpace > 48) {
+ if (Enable5LevelPaging && (SizeOfMemorySpace > 48)) {
NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);
- SizeOfMemorySpace = 48;
}
+ SizeOfMemorySpace = SizeOfMemorySpace > 48 ? 48 : SizeOfMemorySpace;
NumberOfPml4Entries = 1;
if (SizeOfMemorySpace > 39) {
NumberOfPml4Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 39);
--
2.31.1.windows.1
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