[AMD Official Use Only - General] This change follows the Directory/File naming guidance for Processor archs/vendors. Acked-by: Abner Chang <abner.ch...@amd.com>
> -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L > via groups.io > Sent: Sunday, October 30, 2022 9:29 PM > To: devel@edk2.groups.io > Cc: Eric Dong <eric.d...@intel.com>; Ray Ni <ray...@intel.com>; Rahul > Kumar <rahul1.ku...@intel.com>; Daniel Schaefer > <g...@danielschaefer.me> > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 18/30] > UefiCpuPkg/CpuDxe: Add support for RISC-V > > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. > > > REF: > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&data=05%7C01%7Ca > bner.chang%40amd.com%7C3fce7969c0b549d3fb6b08daba7b066e%7C3dd89 > 61fe4884e608e11a82d994e183d%7C0%7C0%7C638027334819795083%7CUnkn > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=iGT3Xy9e%2FVL > cNV%2FnLTW%2BXcQ5eS8Bljhs%2BbGs6Wb25Cw%3D&reserved=0 > > This is copied from > edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe > > Cc: Eric Dong <eric.d...@intel.com> > Cc: Ray Ni <ray...@intel.com> > Cc: Rahul Kumar <rahul1.ku...@intel.com> > Cc: Daniel Schaefer <g...@danielschaefer.me> > Signed-off-by: Sunil V L <suni...@ventanamicro.com> > --- > UefiCpuPkg/CpuDxe/CpuDxe.inf | 10 + > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 199 +++++++++++++ > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 307 ++++++++++++++++++++ > 3 files changed, 516 insertions(+) > > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf > b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 65961813f74b..eddc86a38965 > 100644 > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf > @@ -44,6 +44,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] > MtrrLib > UefiCpuLib > > +[LibraryClasses.RISCV64] > + RiscVSbiLib > + > [Sources.IA32, Sources.X64] > Ia32X64/CpuDxe.c > Ia32X64/CpuDxe.h > @@ -62,6 +65,10 @@ [Sources.X64] > X64/CpuAsm.nasm > X64/PagingAttribute.c > > +[Sources.RISCV64] > + RiscV64/CpuDxe.c > + RiscV64/CpuDxe.h > + > [Protocols] > gEfiCpuArchProtocolGuid ## PRODUCES > gEfiMpServiceProtocolGuid ## PRODUCES > @@ -84,6 +91,9 @@ [Pcd] > gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ## > CONSUMES > gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask ## > CONSUMES > > +[Pcd.RISCV64] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## > CONSUMES > + > [Depex] > TRUE > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h > new file mode 100644 > index 000000000000..49f4e119665a > --- /dev/null > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h > @@ -0,0 +1,199 @@ > +/** @file > + RISC-V CPU DXE module header file. > + > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. > + All rights reserved.<BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef CPU_DXE_H_ > +#define CPU_DXE_H_ > + > +#include <PiDxe.h> > + > +#include <Protocol/Cpu.h> > +#include <Protocol/RiscVBootProtocol.h> #include > +<Library/BaseRiscVSbiLib.h> #include <Library/BaseLib.h> #include > +<Library/CpuExceptionHandlerLib.h> > +#include <Library/DebugLib.h> > +#include <Library/UefiBootServicesTableLib.h> > +#include <Library/UefiDriverEntryPoint.h> > + > +/** > + Flush CPU data cache. If the instruction cache is fully coherent > + with all DMA operations then function can just return EFI_SUCCESS. > + > + @param This Protocol instance structure > + @param Start Physical address to start flushing from. > + @param Length Number of bytes to flush. Round up to chipset > + granularity. > + @param FlushType Specifies the type of flush operation to perform. > + > + @retval EFI_SUCCESS If cache was flushed > + @retval EFI_UNSUPPORTED If flush type is not supported. > + @retval EFI_DEVICE_ERROR If requested range could not be flushed. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuFlushCpuDataCache ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_PHYSICAL_ADDRESS Start, > + IN UINT64 Length, > + IN EFI_CPU_FLUSH_TYPE FlushType > + ); > + > +/** > + Enables CPU interrupts. > + > + @param This Protocol instance structure > + > + @retval EFI_SUCCESS If interrupts were enabled in the CPU > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuEnableInterrupt ( > + IN EFI_CPU_ARCH_PROTOCOL *This > + ); > + > +/** > + Disables CPU interrupts. > + > + @param This Protocol instance structure > + > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuDisableInterrupt ( > + IN EFI_CPU_ARCH_PROTOCOL *This > + ); > + > +/** > + Return the state of interrupts. > + > + @param This Protocol instance structure > + @param State Pointer to the CPU's current interrupt state > + > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. > + @retval EFI_INVALID_PARAMETER State is NULL. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuGetInterruptState ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + OUT BOOLEAN *State > + ); > + > +/** > + Generates an INIT to the CPU. > + > + @param This Protocol instance structure > + @param InitType Type of CPU INIT to perform > + > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be > + seen. > + @retval EFI_DEVICE_ERROR If CPU INIT failed. > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuInit ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_CPU_INIT_TYPE InitType > + ); > + > +/** > + Registers a function to be called from the CPU interrupt handler. > + > + @param This Protocol instance structure > + @param InterruptType Defines which interrupt to hook. IA-32 > + valid range is 0x00 through 0xFF > + @param InterruptHandler A pointer to a function of type > + EFI_CPU_INTERRUPT_HANDLER that is called > + when a processor interrupt occurs. A null > + pointer is an error condition. > + > + @retval EFI_SUCCESS If handler installed or uninstalled. > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a > handler > + for InterruptType was previously installed. > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a > handler for > + InterruptType was not previously installed. > + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType > + is not supported. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuRegisterInterruptHandler ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_EXCEPTION_TYPE InterruptType, > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler > + ); > + > +/** > + Returns a timer value from one of the CPU's internal timers. There is > +no > + inherent time interval between ticks but is a function of the CPU > frequency. > + > + @param This - Protocol instance structure. > + @param TimerIndex - Specifies which CPU timer is requested. > + @param TimerValue - Pointer to the returned timer value. > + @param TimerPeriod - A pointer to the amount of time that passes > + in femtoseconds (10-15) for each increment > + of TimerValue. If TimerValue does not > + increment at a predictable rate, then 0 is > + returned. The amount of time that has > + passed between two calls to GetTimerValue() > + can be calculated with the formula > + (TimerValue2 - TimerValue1) * TimerPeriod. > + This parameter is optional and may be NULL. > + > + @retval EFI_SUCCESS - If the CPU timer count was returned. > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable > timers. > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the > timer. > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue > is NULL. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuGetTimerValue ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN UINT32 TimerIndex, > + OUT UINT64 *TimerValue, > + OUT UINT64 *TimerPeriod OPTIONAL > + ); > + > +/** > + Set memory cacheability attributes for given range of memeory. > + > + @param This Protocol instance structure > + @param BaseAddress Specifies the start address of the > + memory range > + @param Length Specifies the length of the memory range > + @param Attributes The memory cacheability for the memory range > + > + @retval EFI_SUCCESS If the cacheability of that memory range is > + set successfully > + @retval EFI_UNSUPPORTED If the desired operation cannot be done > + @retval EFI_INVALID_PARAMETER The input parameter is not correct, > + such as Length = 0 > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuSetMemoryAttributes ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_PHYSICAL_ADDRESS BaseAddress, > + IN UINT64 Length, > + IN UINT64 Attributes > + ); > + > +#endif > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c > new file mode 100644 > index 000000000000..9f557b776a09 > --- /dev/null > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c > @@ -0,0 +1,307 @@ > +/** @file > + RISC-V CPU DXE driver. > + > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. > + All rights reserved.<BR> > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "CpuDxe.h" > + > +// > +// Global Variables > +// > +STATIC BOOLEAN mInterruptState = FALSE; > +STATIC EFI_HANDLE mCpuHandle = NULL; > + > +EFI_CPU_ARCH_PROTOCOL gCpu = { > + CpuFlushCpuDataCache, > + CpuEnableInterrupt, > + CpuDisableInterrupt, > + CpuGetInterruptState, > + CpuInit, > + CpuRegisterInterruptHandler, > + CpuGetTimerValue, > + CpuSetMemoryAttributes, > + 1, // NumberOfTimers > + 4 // DmaBufferAlignment > +}; > + > +// > +// CPU Arch Protocol Functions > +// > + > +/** > + Flush CPU data cache. If the instruction cache is fully coherent > + with all DMA operations then function can just return EFI_SUCCESS. > + > + @param This Protocol instance structure > + @param Start Physical address to start flushing from. > + @param Length Number of bytes to flush. Round up to chipset > + granularity. > + @param FlushType Specifies the type of flush operation to perform. > + > + @retval EFI_SUCCESS If cache was flushed > + @retval EFI_UNSUPPORTED If flush type is not supported. > + @retval EFI_DEVICE_ERROR If requested range could not be flushed. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuFlushCpuDataCache ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_PHYSICAL_ADDRESS Start, > + IN UINT64 Length, > + IN EFI_CPU_FLUSH_TYPE FlushType > + ) > +{ > + return EFI_SUCCESS; > +} > + > +/** > + Enables CPU interrupts. > + > + @param This Protocol instance structure > + > + @retval EFI_SUCCESS If interrupts were enabled in the CPU > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuEnableInterrupt ( > + IN EFI_CPU_ARCH_PROTOCOL *This > + ) > +{ > + EnableInterrupts (); > + mInterruptState = TRUE; > + return EFI_SUCCESS; > +} > + > +/** > + Disables CPU interrupts. > + > + @param This Protocol instance structure > + > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuDisableInterrupt ( > + IN EFI_CPU_ARCH_PROTOCOL *This > + ) > +{ > + DisableInterrupts (); > + mInterruptState = FALSE; > + return EFI_SUCCESS; > +} > + > +/** > + Return the state of interrupts. > + > + @param This Protocol instance structure > + @param State Pointer to the CPU's current interrupt state > + > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. > + @retval EFI_INVALID_PARAMETER State is NULL. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuGetInterruptState ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + OUT BOOLEAN *State > + ) > +{ > + if (State == NULL) { > + return EFI_INVALID_PARAMETER; > + } > + > + *State = mInterruptState; > + return EFI_SUCCESS; > +} > + > +/** > + Generates an INIT to the CPU. > + > + @param This Protocol instance structure > + @param InitType Type of CPU INIT to perform > + > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be > + seen. > + @retval EFI_DEVICE_ERROR If CPU INIT failed. > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuInit ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_CPU_INIT_TYPE InitType > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +/** > + Registers a function to be called from the CPU interrupt handler. > + > + @param This Protocol instance structure > + @param InterruptType Defines which interrupt to hook. IA-32 > + valid range is 0x00 through 0xFF > + @param InterruptHandler A pointer to a function of type > + EFI_CPU_INTERRUPT_HANDLER that is called > + when a processor interrupt occurs. A null > + pointer is an error condition. > + > + @retval EFI_SUCCESS If handler installed or uninstalled. > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a > handler > + for InterruptType was previously installed. > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a > handler for > + InterruptType was not previously installed. > + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType > + is not supported. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuRegisterInterruptHandler ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_EXCEPTION_TYPE InterruptType, > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler > + ) > +{ > + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); > +} > + > +/** > + Returns a timer value from one of the CPU's internal timers. There is > +no > + inherent time interval between ticks but is a function of the CPU > frequency. > + > + @param This - Protocol instance structure. > + @param TimerIndex - Specifies which CPU timer is requested. > + @param TimerValue - Pointer to the returned timer value. > + @param TimerPeriod - A pointer to the amount of time that passes > + in femtoseconds (10-15) for each increment > + of TimerValue. If TimerValue does not > + increment at a predictable rate, then 0 is > + returned. The amount of time that has > + passed between two calls to GetTimerValue() > + can be calculated with the formula > + (TimerValue2 - TimerValue1) * TimerPeriod. > + This parameter is optional and may be NULL. > + > + @retval EFI_SUCCESS - If the CPU timer count was returned. > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable > timers. > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the > timer. > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue > is NULL. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuGetTimerValue ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN UINT32 TimerIndex, > + OUT UINT64 *TimerValue, > + OUT UINT64 *TimerPeriod OPTIONAL > + ) > +{ > + if (TimerValue == NULL) { > + return EFI_INVALID_PARAMETER; > + } > + > + if (TimerIndex != 0) { > + return EFI_INVALID_PARAMETER; > + } > + > + *TimerValue = (UINT64)RiscVReadTimer (); if (TimerPeriod != NULL) { > + *TimerPeriod = DivU64x32 ( > + 1000000000000000u, > + PcdGet64 (PcdCpuCoreCrystalClockFrequency) > + ); > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Implementation of SetMemoryAttributes() service of CPU Architecture > Protocol. > + > + This function modifies the attributes for the memory region specified > + by BaseAddress and Length from their current attributes to the attributes > specified by Attributes. > + > + @param This The EFI_CPU_ARCH_PROTOCOL instance. > + @param BaseAddress The physical address that is the start address of > a > memory region. > + @param Length The size in bytes of the memory region. > + @param Attributes The bit mask of attributes to set for the memory > region. > + > + @retval EFI_SUCCESS The attributes were set for the memory > region. > + @retval EFI_ACCESS_DENIED The attributes for the memory resource > range specified by > + BaseAddress and Length cannot be modified. > + @retval EFI_INVALID_PARAMETER Length is zero. > + Attributes specified an illegal combination > of attributes that > + cannot be set together. > + @retval EFI_OUT_OF_RESOURCES There are not enough system > resources to modify the attributes of > + the memory resource range. > + @retval EFI_UNSUPPORTED The processor does not support one or > more bytes of the memory > + resource range specified by BaseAddress and > Length. > + The bit mask of attributes is not support > for the memory > resource > + range specified by BaseAddress and Length. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuSetMemoryAttributes ( > + IN EFI_CPU_ARCH_PROTOCOL *This, > + IN EFI_PHYSICAL_ADDRESS BaseAddress, > + IN UINT64 Length, > + IN UINT64 Attributes > + ) > +{ > + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", > +__FUNCTION__)); > + return EFI_SUCCESS; > +} > + > +/** > + Initialize the state information for the CPU Architectural Protocol. > + > + @param ImageHandle Image handle this driver. > + @param SystemTable Pointer to the System Table. > + > + @retval EFI_SUCCESS Thread can be successfully created > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure > + @retval EFI_DEVICE_ERROR Cannot create the thread > + > +**/ > +EFI_STATUS > +EFIAPI > +InitializeCpu ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + EFI_STATUS Status; > + > + InitializeCpuExceptionHandlers(NULL); > + > + // > + // Make sure interrupts are disabled > + // > + DisableInterrupts (); > + > + // > + // Install CPU Architectural Protocol > + // > + Status = gBS->InstallMultipleProtocolInterfaces ( > + &mCpuHandle, > + &gEfiCpuArchProtocolGuid, > + &gCpu, > + NULL > + ); > + ASSERT_EFI_ERROR (Status); > + return Status; > +} > -- > 2.38.0 > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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