On Thu, 22 Sept 2022 at 07:55, Gerd Hoffmann <kra...@redhat.com> wrote:
>
> Traditional q35 memory layout is 2.75 GB of low memory, leaving room
> for the pcie mmconfig at 0xb0000000 and the 32-bit pci mmio window at
> 0xc0000000. Because of that OVMF tags the memory range above
> 0xb0000000 as uncachable via mtrr.
>
> A while ago qemu started to gigabyte-align memory by default (to make
> huge pages more effective) and q35 uses only 2G of low memory in that
> case. Which effectively makes the 32-bit pci mmio window start at
> 0x80000000.
>
> This patch updates the mtrr setup code accordingly.
>
> Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Ard Biesheuvel <a...@kernel.org>
Merged as #3425
> ---
> OvmfPkg/Library/PlatformInitLib/MemDetect.c | 26 ++++++++++++++-------
> 1 file changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
> b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
> index 942eaf89cfcf..d1a4f4b20791 100644
> --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
> +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
> @@ -55,15 +55,25 @@ PlatformQemuUc32BaseInitialization (
> }
>
> if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
> - //
> - // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
> - // starts at PcdPciExpressBaseAddress. The platform DSC is responsible
> for
> - // setting PcdPciExpressBaseAddress such that describing the
> - // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
> - // variable MTRRs (preferably 1 or 2).
> - //
> + LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
> ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
> - PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress);
> + ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= LowerMemorySize);
> +
> + if (LowerMemorySize <= BASE_2GB) {
> + // Newer qemu with gigabyte aligned memory,
> + // 32-bit pci mmio window is 2G -> 4G then.
> + PlatformInfoHob->Uc32Base = BASE_2GB;
> + } else {
> + //
> + // On q35, the 32-bit area that we'll mark as UC, through variable
> MTRRs,
> + // starts at PcdPciExpressBaseAddress. The platform DSC is responsible
> for
> + // setting PcdPciExpressBaseAddress such that describing the
> + // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
> + // variable MTRRs (preferably 1 or 2).
> + //
> + PlatformInfoHob->Uc32Base = (UINT32)PcdGet64
> (PcdPciExpressBaseAddress);
> + }
> +
> return;
> }
>
> --
> 2.37.3
>
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