Gerd, I have some comments in line.
With those fixes,
Reviewed-by: Abner Chang <abner.ch...@hpe.com>
> -----Original Message-----
> From: Gerd Hoffmann <kra...@redhat.com>
> Sent: Friday, April 22, 2022 3:37 PM
> To: devel@edk2.groups.io
> Cc: Pawel Polawski <ppola...@redhat.com>; Ard Biesheuvel
> <ardb+tianoc...@kernel.org>; Liming Gao <gaolim...@byosoft.com.cn>;
> Hao A Wu <hao.a...@intel.com>; Ray Ni <ray...@intel.com>; Oliver Steffen
> <ostef...@redhat.com>; Leif Lindholm <quic_llind...@quicinc.com>; Jordan
> Justen <jordan.l.jus...@intel.com>; Jiewen Yao <jiewen....@intel.com>;
> Gerd Hoffmann <kra...@redhat.com>; Chang, Abner (HPS SW/FW
> Technologist) <abner.ch...@hpe.com>; Jian J Wang
> <jian.j.w...@intel.com>
> Subject: [PATCH v5 2/6] OvmfPkg/FdtPciHostBridgeLib: io range is not
> mandatory
>
> io range is not mandatory according to pcie spec,
> so allow host bridges without io address space.
>
> Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
> ---
> .../FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 45 ++++++++++---------
> 1 file changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> b/OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> index 98828e0b262b..823ea47c80a3 100644
> --- a/OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> +++ b/OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> @@ -292,13 +292,8 @@ ProcessPciHost (
> }
> }
>
> - if ((*IoSize == 0) || (*Mmio32Size == 0)) {
> - DEBUG ((
> - DEBUG_ERROR,
> - "%a: %a space empty\n",
> - __FUNCTION__,
> - (*IoSize == 0) ? "IO" : "MMIO32"
> - ));
> + if (*Mmio32Size == 0) {
> + DEBUG ((DEBUG_ERROR, "%a: MMIO32 space empty\n",
> __FUNCTION__));
> return EFI_PROTOCOL_ERROR;
> }
>
> @@ -333,13 +328,15 @@ ProcessPciHost (
> return Status;
> }
>
> - //
> - // Map the MMIO window that provides I/O access - the PCI host bridge
> code
> - // is not aware of this translation and so it will only map the I/O view
> - // in the GCD I/O map.
> - //
> - Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize);
> - ASSERT_EFI_ERROR (Status);
> + if (*IoSize) {
I think I missed this in the previous review.
According to coding standard, this line should be
if (*IoSize != 0)
> + //
> + // Map the MMIO window that provides I/O access - the PCI host bridge
> code
> + // is not aware of this translation and so it will only map the I/O view
> + // in the GCD I/O map.
> + //
> + Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize);
> + ASSERT_EFI_ERROR (Status);
> + }
>
> return Status;
> }
> @@ -413,17 +410,21 @@ PciHostBridgeGetRootBridges (
>
> AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
>
> - Io.Base = IoBase;
> - Io.Limit = IoBase + IoSize - 1;
> + if (IoSize) {
Same here
> + Io.Base = IoBase;
> + Io.Limit = IoBase + IoSize - 1;
> + } else {
> + Io.Base = MAX_UINT64;
> + Io.Limit = 0;
> + }
> +
> Mem.Base = Mmio32Base;
> Mem.Limit = Mmio32Base + Mmio32Size - 1;
>
> - if (sizeof (UINTN) == sizeof (UINT64)) {
> - MemAbove4G.Base = Mmio64Base;
> - MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;
> - if (Mmio64Size > 0) {
> - AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
> - }
> + if ((sizeof (UINTN) == sizeof (UINT64)) && Mmio64Size) {
Same here for Mmio64Size.
Abner
> + MemAbove4G.Base = Mmio64Base;
> + MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;
> + AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
> } else {
> //
> // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit
> --
> 2.35.1
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