REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
Ensure bit3:0 of NewStack is aligned with bit3:0 of OldStack for X64
before switching stack. Otherwise, RSP may not be aligned to a 16-byte
boundary after returning from SecTemporaryRamSupport.
Cc: Chasel Chiu <chasel.c...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Cc: Ashraf Ali S <ashraf.al...@intel.com>
Signed-off-by: Ted Kuo <ted....@intel.com>
---
IntelFsp2Pkg/FspSecCore/SecMain.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index d376fb8361..f93e2d2ff7 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -258,6 +258,14 @@ SecTemporaryRamSupport (
NewStack = (VOID *)(UINTN)PermanentMemoryBase;
}
+ //
+ // Ensure bit3:0 of NewStack is aligned with bit3:0 of OldStack for X64
before switching stack.
+ // Otherwise, RSP may not be aligned to a 16-byte boundary after returning
from SecTemporaryRamSupport.
+ //
+ if ((sizeof (UINTN) == sizeof (UINT64)) && (((UINTN)NewStack & 0x0F) !=
((UINTN)OldStack & 0x0F))) {
+ NewStack = (VOID *)((UINTN)NewStack - 8);
+ }
+
//
// Migrate Heap
//
--
2.16.2.windows.1
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