On Wed, 23 Feb 2022 at 19:14, Ashish Singhal <ashishsin...@nvidia.com> wrote: > > Ard, > > During PrePi, I setup the initial memory map by calling into ArmConfigureMmu > function with my memory table where device memory regions have attribute of > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE and DRAM regions have attribute of > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK. > > For device memory, XN bit is set by ArmMemoryAttributeToPageAttribute > function. After PrePi, when I add a region of memory to device memory from a > DXE driver, I call gDS->AddMemorySpace with EfiGcdMemoryTypeMemoryMappedIo > and EFI_MEMORY_UC | EFI_MEMORY_RUNTIME followed by > gDS->SetMemorySpaceAttributes with EFI_MEMORY_UC. > > Please let me know in case I have still not understood your question. >
This all looks ok. But the real question is whether the address that the speculative access targets is mapped using the XN attribute or not, so you will need to find a way to check that. So there are a couple of options: - The XN attribute is set correctly, but the CPU is speculatively fetching instructions anyway. This would imply a severe hardware bug, and flushing the I-cache is unlikely to make a difference. - The speculative access is not the result of an instruction fetch, in which case I-cache maintenance is unlikely to help either. - The XN bit is not being set correctly, and so the MMU code needs to be fixed. Papering over this by adding I-cache maintenance doesn't seem the best course of action tbh. -- Ard. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#86927): https://edk2.groups.io/g/devel/message/86927 Mute This Topic: https://groups.io/mt/89309504/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
