On Thu, Jan 20, 2022 at 06:10:14PM +0100, Nicolas Ojeda Leon wrote: > Create the Hardware Info library base together with the specifics to > describe PCI Host Bridges. > > The Hardware Info library is intended to be used for disclosing > non-discoverable hardware information from the host to the guest in > Ovmf platforms. Core functionality will provide the possibility to > parse information from a generic BLOB into runtime structures. The > library is conceived in a generic way so that further hardware > elements can also be described using it. For such purpose the length > of the BLOB is not restricted but instead regarded as a sequence of > header-info elements that allow the parsing during runtime. The first > type of hardware defined will be PCI host bridges, providing the > possibility to define multiple and specify the resources each of them > can use. This enables the guest firmware to configure PCI resources > properly. Having the size of each individual element favors the reuse > of a single interface to convey descriptions of an arbitrary number > of heterogenous hardware elements. Furthermore, flexible access > mechanisms coupled with the size will grant the possibility of > interpreting them in a single run. > > Define the base types of the generic Hardware Info library to parse > heterogeneous data. Also provide the specific changes to support > PCI host bridges as the first hardware type supported by the > library. > Additionally, define the HOST_BRIDGE_INFO structure to describe PCI > host bridges along with the functionality to parse such information > into proper structures used by the PCI driver in a centralized manner > and taking care of versioning. > > As an example and motivation, the library will be used to define > multiple PCI host bridges for complex platforms that require it. > The first means of transportation that will be used is going to be > fw-cfg, over which a stream of bytes will be transferred and later > parsed by the hardware info library. Accordingly, the PCI driver > will make use of these host bridges definitions to populate the > list of Root Bridges and proceed with the configuration and discovery > of underlying hardware components. > > As mentioned before, the binary data to be parsed by the Hardware > Info library should be organized as a sequence of Header-element > pairs in which the header describes the type and size of the associated > element that comes right after it. As an illustration, to provide > inforation of 3 host bridges the data, conceptually, would look > like this: > > Header PCI Host Bridge (type and size) # 1 > PCI Host Bridge info # 1 > Header PCI Host Bridge (type and size) # 2 > PCI Host Bridge info # 2 > Header PCI Host Bridge (type and size) # 3 > PCI Host Bridge info # 3 > > Cc: Alexander Graf <g...@amazon.de> > Cc: Gerd Hoffmann <kra...@redhat.com> > > Signed-off-by: Nicolas Ojeda Leon <ncol...@amazon.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com> -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85918): https://edk2.groups.io/g/devel/message/85918 Mute This Topic: https://groups.io/mt/88565403/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
