microvm places the 64bit mmio space at the end of the physical address
space. So mPhysMemAddressWidth must be correct, otherwise the pci host
bridge setup throws an error because it thinks the 64bit mmio window is
not addressable.
On microvm we can simply use standard cpuid to figure the address width
because the host-phys-bits option (-cpu ${name},host-phys-bits=on) is
forced to be enabled. Side note: For 'pc' and 'q35' this is not the
case for backward compatibility reasons.
Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
---
OvmfPkg/PlatformPei/MemDetect.c | 21 +++++++++++++++++++++
OvmfPkg/PlatformPei/Platform.c | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index f87a6f48a1bf..571d02d628f1 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -552,6 +552,27 @@ AddressWidthInitialization (
{
UINT64 FirstNonAddress;
+ if (mHostBridgeDevId == 0xffff /* microvm */) {
+ UINT32 RegEax;
+
+ /* NOTE: microvm phys-bits are reliable. */
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+ if (RegEax >= 0x80000008) {
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+ mPhysMemAddressWidth = (UINT8)RegEax;
+ } else {
+ mPhysMemAddressWidth = 36;
+ }
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: microvm: phys-bits is %d\n",
+ __FUNCTION__,
+ mPhysMemAddressWidth
+ ));
+ return;
+ }
+
//
// As guest-physical memory size grows, the permanent PEI RAM requirements
// are dominated by the identity-mapping page tables built by the DXE IPL.
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 27ada0c17577..b8cc0c31dd64 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -821,12 +821,12 @@ InitializePlatform (
S3Verification ();
BootModeInitialization ();
- AddressWidthInitialization ();
//
// Query Host Bridge DID
//
mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+ AddressWidthInitialization ();
MaxCpuCountInitialization ();
--
2.34.1
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