(This is migrated from edk2-platforms:Silicon/RISC-V) NULL instance of RISC-V platform timer library.
Signed-off-by: Abner Chang <abner.ch...@hpe.com> Co-authored-by: Gilbert Chen <gilbert.c...@hpe.com> Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org> Cc: Leif Lindholm <leif.lindh...@linaro.org> Cc: Gilbert Chen <gilbert.c...@hpe.com> --- .../RiscVPlatformTimerLib.inf | 35 ++++++++++++++++ .../RiscVPlatformTimerLibNull.S | 40 +++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf new file mode 100644 index 0000000000..6bf168c72e --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf @@ -0,0 +1,35 @@ +## @file +# RISC-V CPU lib to override timer mechanism for U500 platform. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = RiscVPlatformTimerLibNull + FILE_GUID = 93FDB133-476E-4726-A65D-C10D5C9A68DE + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVPlatformTimerLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + +[Sources.RISCV64] + RiscVPlatformTimerLibNull.S + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + + + + diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S new file mode 100644 index 0000000000..815ab06bac --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S @@ -0,0 +1,40 @@ +//------------------------------------------------------------------------------ +// +// Null instance of Timer CSR functions. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ +#include <Base.h> + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimer) +.global ASM_PFX(RiscVSetMachineTimerCmp) +.global ASM_PFX(RiscVReadMachineTimerCmp) + +// +// Read machine timer CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimer): + ret + +// +// Set machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVSetMachineTimerCmp): + ret + +// +// Read machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVReadMachineTimerCmp): + ret -- 2.31.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85352): https://edk2.groups.io/g/devel/message/85352 Mute This Topic: https://groups.io/mt/88278524/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
