On 1/7/22 11:04 AM, Peter Gonda wrote:
The SEV-ES bit of Fn800-001F[EAX] - Bit 3 is used for a host to determine support for running SEV-ES guests. It should not be checked by a guest to determine if it is running under SEV-ES. The guest should use the SEV_STATUS MSR Bit 1 to determine if SEV-ES is enabled.
Worth mentioning in the commit message that this check wasn't part of the original SEV-ES support (Fixes: a91b700e385e7484ab7286b3ba7ea2efbd59480e tag?), so this is really a compatibility thing, and that this makes the check consistent with the Linux kernel.
Thanks, Tom
Cc: James Bottomley <j...@linux.ibm.com> Cc: Min Xu <min.m...@intel.com> Cc: Jiewen Yao <jiewen....@intel.com> Cc: Tom Lendacky <thomas.lenda...@amd.com> Cc: Jordan Justen <jordan.l.jus...@intel.com> Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org> Cc: Laszlo Ersek <ler...@redhat.com> Cc: Erdem Aktas <erdemak...@google.com> Cc: Marc Orr <marc...@google.com> Cc: Brijesh Singh <brijesh.si...@amd.com> Cc: Jim Mattson <jmatt...@google.com> Signed-off-by: Peter Gonda <pgo...@google.com> --- OvmfPkg/ResetVector/Ia32/AmdSev.asm | 8 -------- 1 file changed, 8 deletions(-) diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32/AmdSev.asm index 1f827da3b9..77692db27e 100644 --- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm +++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm @@ -265,14 +265,6 @@ CheckSevFeatures: ; Set the work area header to indicate that the SEV is enabled mov byte[WORK_AREA_GUEST_TYPE], 1- ; Check for SEV-ES memory encryption feature:- ; CPUID Fn8000_001F[EAX] - Bit 3 - ; CPUID raises a #VC exception if running as an SEV-ES guest - mov eax, 0x8000001f - cpuid - bt eax, 3 - jnc GetSevEncBit - ; Check if SEV-ES is enabled ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled) mov ecx, SEV_STATUS_MSR
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